Christopher W Read

US Patent:

6370558, Apr 9, 2002

Filed:

Oct 3, 2000

Appl. No.:

09/678746

Inventors:

Karl M. Guttag - Missouri City TX
Christopher J. Read - Houston TX
Keith Balmer - Bedford, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1500

US Classification:

708603

Abstract:

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products.

US Patent:

7389317, Jun 17, 2008

Filed:

Apr 9, 2002

Appl. No.:

10/119254

Inventors:

Karl M. Guttag - Missouri City TX, US
Christopher J. Read - Houston TX, US
Keith Balmer - Bedford, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 7/52

US Classification:

708620, 708625

Abstract:

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products.

US Patent:

20080077771, Mar 27, 2008

Filed:

Oct 31, 2007

Appl. No.:

11/930652

Inventors:

Karl Guttag - Missouri City TX, US
Christopher Read - Houston TX, US
Keith Balmer - Bedford, GB

International Classification:

G06F 9/30

US Classification:

712204000, 712E09028

Abstract:

This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit () includes a multiplication unit () and an arithmetic logic unit (). The data unit () may include a barrel rotator () for one input of the arithmetic logic unit (). The rotated data may be stored in the first destination register instead of the multiply result. The address unit () operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register (). The status register () is set by a prior output of the arithmetic logic unit () and the instruction may specify some of the status bits protect from change. The address unit () preferably includes a plurality of base address registers (), a full adder () and a left shifter (). The full adder () may add an index as scaled by the left shifter to the base address or subtract the scaled index from the base address. The full adder () output may update the base address register (), either before supply of the address or following supply of the address. The index may be recalled from an index register () or an immediate value. In the preferred embodiment of this invention, the data unit () including the data registers (), the multiplication unit () and the arithmetic logic unit (), the address unit () and the instruction decode logic () are embodied in at least one digital image/graphics processor () as a part of a multiprocessor () formed in a single integrated circuit used in image processing.

US Patent:

59616350, Oct 5, 1999

Filed:

Nov 30, 1993

Appl. No.:

8/160111

Inventors:

Karl M. Guttag - Missouri City TX
Keith Balmer - Bedford, GB
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX
Jeremiah E. Golston - Sugar Land TX
Sydney W. Poland - Kary TX
Nicholas Ing-Simmons - Huntington, GB
Phillip Moyse - Bedford, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 930

US Classification:

712221

Abstract:

A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2. sup. N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer.

US Patent:

60321709, Feb 29, 2000

Filed:

Apr 20, 1998

Appl. No.:

9/063318

Inventors:

Karl M. Guttag - Missouri City TX
Christopher J. Read - Houston TX
Keith Balmer - Bedford, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 752
G06F 738

US Classification:

708620

Abstract:

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus.

US Patent:

56511272, Jul 22, 1997

Filed:

Mar 8, 1994

Appl. No.:

8/209123

Inventors:

Robert J. Gove - Plano TX
Karl M. Guttag - Sugarland TX
Keith Balmer - Bedford, GB2
Christopher J. Read - Houston TX
Iain Robertson - Bedfordshire, GB2
Nicholas Ing Simmons - Huntingdon, GB2

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 9126
G06F 1200
G06F 934
G06F 1214

US Classification:

395412

Abstract:

This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table.

US Patent:

61167681, Sep 12, 2000

Filed:

Nov 30, 1993

Appl. No.:

8/160299

Inventors:

Karl M. Guttag - Missouri City TX
Keith Balmer - Bedford, GB
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX
Jeremiah E. Golston - Sugar Land TX
Sydney W. Poland - Kary TX
Nicholas Ing-Simmons - Huntingdon, GB
Phillip Moyse - Bromham, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 736

US Classification:

36471607

Abstract:

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2. sup. N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

US Patent:

59601930, Sep 28, 1999

Filed:

Aug 27, 1997

Appl. No.:

8/922726

Inventors:

Karl M. Guttag - Missouri City TX
Christopher J. Read - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 900

US Classification:

395562

Abstract:

A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between corresponding numbers of the first and second sets. This difference is either added to or subtracted from a running sum based upon its sign. This is repeated for all number pairs. Preferably, the initial subtraction sets a status bit in a flag register (211) which controls the selection of addition or subtraction. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is preferably stored and later added to the running sum to recover the most significant overflow bits. This technique is preferably practiced using an arithmetic logic unit (230) that can be split into plural independent sections (301, 302, 303, 304). A multiple flags register (211) stores status bits of corresponding sections controlling the conditional addition to or subtraction from a like plurality of running sums.