Chuan W Lin

US Patent:

6544853, Apr 8, 2003

Filed:

Jan 18, 2002

Appl. No.:

10/050528

Inventors:

Chuan Lin - Poughquag NY

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 2148

US Classification:

438305, 438528, 438535

Abstract:

A process of fabricating a p-type metal oxide semiconductor to affect reduction of negative bias temperature instability (NBTI) in the formed p-type metal oxide semiconductor structure by: a) forming a gate on a gate oxide in a substrate; b) forming a spacer on a sidewall of the gate; c) forming a source/drain extension beside the gate oxide in the substrate or forming a lightly doped drain (LDD) implantation into the gate oxide; and d) implanting F between the gate oxide and the source drain extension at a sufficiently large tilted angle and in sufficient amount to affect reduction of negative bias temperature instability characteristics lower than without F implantation.

US Patent:

6780730, Aug 24, 2004

Filed:

Jan 31, 2002

Appl. No.:

10/059321

Inventors:

Chuan Lin - Poughquag NY

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 2176

US Classification:

438424, 438246, 438389, 438433, 438527

Abstract:

In a process of fabricating a narrow channel width PMOSFET device, the improvement of affecting reduction of negative bias temperature instability by use of F side wall implantation, comprising: a) forming a shallow trench isolation (STI) region in a substrate; b) forming a gate on a gate oxide in the substrate; c) forming a liner layer in said shallow trench isolation region and subjecting the liner layer to oxidation to form a STI liner oxidation layer; d) implanting F into side walls of the STI liner oxidation layer at a large tilted angle in sufficient amounts to affect reduction of negative bias temperature instability after a high density plasma fill of the STI F implanted liner oxidation layer; and e) filling the STI F implanted structure from step d) with a high density plasma (HDP) fill to affect reduction of negative bias temperature instability.

US Patent:

7939440, May 10, 2011

Filed:

Jun 15, 2005

Appl. No.:

11/152375

Inventors:

Shibly S. Ahmed - San Jose CA, US
Jun Kang - San Jose CA, US
Hsiao-Han Thio - Santa Clara CA, US
Imran Khan - Santa Clara CA, US
Chuan Lin - Sunnyvale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/425
H01L 21/44

US Classification:

438529, 438527, 438682, 257E21619

Abstract:

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

US Patent:

8536011, Sep 17, 2013

Filed:

Mar 29, 2011

Appl. No.:

13/074836

Inventors:

Shibly S. Ahmed - San Jose CA, US
Jun Kang - San Jose CA, US
Hsiao-Han Thio - Santa Clara CA, US
Imran Khan - Santa Clara CA, US
Chuan Lin - Sunnyvale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/336
H01L 21/44
H01L 29/788

US Classification:

438307, 257E21619, 257316, 438682

Abstract:

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

US Patent:

8598005, Dec 3, 2013

Filed:

Jul 18, 2011

Appl. No.:

13/185390

Inventors:

Simon Siu-Sing Chan - Saratoga CA, US
Hidehiko Shiraiwa - San Jose CA, US
Chuan Lin - Cupertino CA, US
Lei Xue - Milpitas CA, US
Kenichi Ohtsuka - Sunnyvale CA, US
Angela Tai Hui - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/772

US Classification:

438301, 438257, 438258, 438275, 438276, 438279, 257391, 257392, 257E21626

Abstract:

A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.

US Patent:

20030013214, Jan 16, 2003

Filed:

Jul 13, 2001

Appl. No.:

09/905386

Inventors:

Chuan Lin - Poughquag NY, US

Assignee:

Infineon Technologies North America Corp.

International Classification:

H01L021/66

US Classification:

438/017000

Abstract:

Disclosed is a method of testing a dielectric, comprising setting a reference current below a breakdown current of the dielectric, applying a stress voltage to the dielectric below a breakdown voltage of the dielectric and measuring a stress current resulting therefrom, incrementally increasing said stress voltage until said measured stress current exceeds said reference current.

US Patent:

20100114767, May 6, 2010

Filed:

Oct 31, 2008

Appl. No.:

12/262493

Inventors:

Chuan Bin Lin - Richardson TX, US
Tim Byrd - Charlotte NC, US
Rhonna J. Clark - Charlotte NC, US
Helen elaine Sarris - Burlington NJ, US
Dan Shnowske - Waxahachie TX, US
William S. Treadwell - Charlotte NC, US
Mian Zhou - Dallas TX, US

Assignee:

Bank of America Corp. - Charlotte NC

International Classification:

G06Q 40/00
G06F 3/12

US Classification:

705 41, 705 35, 358 115

Abstract:

Apparatus and methods for providing a card that has a stored value. The apparatus and methods may involve offering the card to a customer, applying branding information to the card, charging a customer account for the value, and dispensing the card. The stored value card may be provided by a machine to a customer. The machine may be a financial institution automated teller machine (ATM). The ATM may transmit instructions to transfer funds from the customer's to one or more of the financial institution's retail partners. The ATM may apply visual information to the card. The visual information may include branding information, a message or any other suitable information.

US Patent:

20120241871, Sep 27, 2012

Filed:

Mar 24, 2011

Appl. No.:

13/071385

Inventors:

Chuan Lin - Cupertino CA, US
Hidehiko Shiraiwa - San Jose CA, US
Bradley Marc Davis - Mountain View CA, US
Lei Xue - Milpitas CA, US
Simon S. Chan - Saratoga CA, US
Kenichi Ohtsuka - Sunnyvale CA, US
Angela T. Hui - Fremont CA, US
Scott Allan Bell - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/788
H01L 21/28

US Classification:

257392, 438592, 257E21158, 257E293

Abstract:

A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.