Chuan Hung Lin

US Patent:

7939440, May 10, 2011

Filed:

Jun 15, 2005

Appl. No.:

11/152375

Inventors:

Shibly S. Ahmed - San Jose CA, US
Jun Kang - San Jose CA, US
Hsiao-Han Thio - Santa Clara CA, US
Imran Khan - Santa Clara CA, US
Chuan Lin - Sunnyvale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/425
H01L 21/44

US Classification:

438529, 438527, 438682, 257E21619

Abstract:

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

US Patent:

8536011, Sep 17, 2013

Filed:

Mar 29, 2011

Appl. No.:

13/074836

Inventors:

Shibly S. Ahmed - San Jose CA, US
Jun Kang - San Jose CA, US
Hsiao-Han Thio - Santa Clara CA, US
Imran Khan - Santa Clara CA, US
Chuan Lin - Sunnyvale CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/336
H01L 21/44
H01L 29/788

US Classification:

438307, 257E21619, 257316, 438682

Abstract:

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

US Patent:

8598005, Dec 3, 2013

Filed:

Jul 18, 2011

Appl. No.:

13/185390

Inventors:

Simon Siu-Sing Chan - Saratoga CA, US
Hidehiko Shiraiwa - San Jose CA, US
Chuan Lin - Cupertino CA, US
Lei Xue - Milpitas CA, US
Kenichi Ohtsuka - Sunnyvale CA, US
Angela Tai Hui - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/772

US Classification:

438301, 438257, 438258, 438275, 438276, 438279, 257391, 257392, 257E21626

Abstract:

A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.

US Patent:

20120241871, Sep 27, 2012

Filed:

Mar 24, 2011

Appl. No.:

13/071385

Inventors:

Chuan Lin - Cupertino CA, US
Hidehiko Shiraiwa - San Jose CA, US
Bradley Marc Davis - Mountain View CA, US
Lei Xue - Milpitas CA, US
Simon S. Chan - Saratoga CA, US
Kenichi Ohtsuka - Sunnyvale CA, US
Angela T. Hui - Fremont CA, US
Scott Allan Bell - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/788
H01L 21/28

US Classification:

257392, 438592, 257E21158, 257E293

Abstract:

A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.