Chuan Lin Lin

US Patent:

6544853, Apr 8, 2003

Filed:

Jan 18, 2002

Appl. No.:

10/050528

Inventors:

Chuan Lin - Poughquag NY

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 2148

US Classification:

438305, 438528, 438535

Abstract:

A process of fabricating a p-type metal oxide semiconductor to affect reduction of negative bias temperature instability (NBTI) in the formed p-type metal oxide semiconductor structure by: a) forming a gate on a gate oxide in a substrate; b) forming a spacer on a sidewall of the gate; c) forming a source/drain extension beside the gate oxide in the substrate or forming a lightly doped drain (LDD) implantation into the gate oxide; and d) implanting F between the gate oxide and the source drain extension at a sufficiently large tilted angle and in sufficient amount to affect reduction of negative bias temperature instability characteristics lower than without F implantation.

US Patent:

6780730, Aug 24, 2004

Filed:

Jan 31, 2002

Appl. No.:

10/059321

Inventors:

Chuan Lin - Poughquag NY

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 2176

US Classification:

438424, 438246, 438389, 438433, 438527

Abstract:

In a process of fabricating a narrow channel width PMOSFET device, the improvement of affecting reduction of negative bias temperature instability by use of F side wall implantation, comprising: a) forming a shallow trench isolation (STI) region in a substrate; b) forming a gate on a gate oxide in the substrate; c) forming a liner layer in said shallow trench isolation region and subjecting the liner layer to oxidation to form a STI liner oxidation layer; d) implanting F into side walls of the STI liner oxidation layer at a large tilted angle in sufficient amounts to affect reduction of negative bias temperature instability after a high density plasma fill of the STI F implanted liner oxidation layer; and e) filling the STI F implanted structure from step d) with a high density plasma (HDP) fill to affect reduction of negative bias temperature instability.

US Patent:

7980464, Jul 19, 2011

Filed:

Dec 23, 2008

Appl. No.:

12/343036

Inventors:

Helen Sarris - Burlington NJ, US
Timothy B. Byrd - Charlotte NC, US
Rhonna J. Clark - Charlotte NC, US
Chuan Bin Lin - Richardson TX, US
Daniel P. Shnowske - Waxahachie TX, US
William Treadwell - Addison TX, US
Mian Zhou - Dallas TX, US

Assignee:

Bank of America Corporation - Charlotte NC

International Classification:

G06Q 40/00
G07D 11/00
G07F 19/00

US Classification:

235379, 705 43, 705 44

Abstract:

Systems and methods are provided for protecting against bank card fraud and related crimes by providing a distress/fraud trigger at bank card machines, such as automated teller machines and point-of-sale terminals. The trigger initiates certain heightened-security processes designed to stop the crime, control damage, and help apprehend the criminal. For example, in one embodiment, the trigger involves the cardholder inputting a “panic” personal identification code into the bank card machine. The panic personal identification code indicates to a party involved in the bank card transaction that a fraudulent transaction may be taking place. The heightened-security processes may include, for example, displaying that the bank card machine is out-of-order, dispensing money with a GPS tracking device, requesting additional identification steps, instituting delay tactics, notifying on-site personnel, or forwarding audio or video information from the bank card machine to a bank's command center in real time or near real time.

US Patent:

20030013214, Jan 16, 2003

Filed:

Jul 13, 2001

Appl. No.:

09/905386

Inventors:

Chuan Lin - Poughquag NY, US

Assignee:

Infineon Technologies North America Corp.

International Classification:

H01L021/66

US Classification:

438/017000

Abstract:

Disclosed is a method of testing a dielectric, comprising setting a reference current below a breakdown current of the dielectric, applying a stress voltage to the dielectric below a breakdown voltage of the dielectric and measuring a stress current resulting therefrom, incrementally increasing said stress voltage until said measured stress current exceeds said reference current.

US Patent:

6472301, Oct 29, 2002

Filed:

Oct 19, 1999

Appl. No.:

09/421161

Inventors:

Chuan Lin - Poughquag NY
Thomas Schafbauer - Wappingers Falls NY
Paul Wensley - Wappingers Falls NY

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 218242

US Classification:

438524, 438433, 438527, 438224

Abstract:

A method (see e. g. , FIG. ) of fabricating a semiconductor device includes forming a trench in a semiconductor body. A dielectric layer is formed within the trench. Dielectric layer lines the sidewall and, possibly, the bottom portions of the trench in a manner where the thickness of the dielectric at the sidewall is greater than the thickness of the dielectric at the bottom. A dopant can then be implanted into the semiconductor body beneath the trench.