Chun Wah Wong

US Patent:

8637993, Jan 28, 2014

Filed:

Apr 23, 2012

Appl. No.:

13/453043

Inventors:

Chun Yu Wong - Clifton Park NY, US
Ramakanth Alapati - Rexford NY, US
Teck Jung Tang - Ballston Lake NY, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 23/48
H01L 29/10
H01L 23/52

US Classification:

257774, 257 43, 257778

Abstract:

A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.

US Patent:

20060185019, Aug 17, 2006

Filed:

Feb 11, 2005

Appl. No.:

11/056020

Inventors:

Chun Wong - Los Angeles CA, US

International Classification:

H04N 7/16

US Classification:

726026000

Abstract:

A method and system for observational data collection (ODC), such as field audit and survey data collection, comprises a method, computer system and computer program for inputting into one or more configuration forms first information specifying content and format for an ODC form and one or more authorized users; and publishing at least a portion of the ODC form to one or more of the authorized users. The system and method provide an efficient and accurate alternative to ODC as compared to known approaches.

US Patent:

20210111065, Apr 15, 2021

Filed:

Oct 9, 2019

Appl. No.:

16/596814

Inventors:

- Santa Clara CA, US
Wei Hong - Clifton Park NY, US
Chun Yu Wong - Clifton Park NY, US
Haiting Wang - Clifton Park NY, US
Liu Jiang - Clifton Park NY, US

International Classification:

H01L 21/762
H01L 27/12

Abstract:

A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

US Patent:

20200098688, Mar 26, 2020

Filed:

Sep 25, 2018

Appl. No.:

16/140545

Inventors:

- Grand Cayman, KY
RUILONG XIE - Schenectady NY, US
NAN FU - Ballston Lake NY, US
CHUN YU WONG - Clifton Park NY, US

International Classification:

H01L 23/528
H01L 21/768
H01L 21/027
H01L 23/532
H01L 23/522
H01L 21/285

Abstract:

A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.

US Patent:

20190371796, Dec 5, 2019

Filed:

May 31, 2018

Appl. No.:

15/994231

Inventors:

- GRAND CAYMAN, KY
Garo Jacques Derderian - Saratoga Springs NY, US
Laertis Economikos - Wappingers Falls NY, US
Chun Yu Wong - Ballston Lake NY, US
Jiehui Shu - Clifton Park NY, US
Shesh Mani Pandey - Saratoga Springs NY, US

Assignee:

GLOBALFOUNDRIES INC. - GRAND CAYMAN

International Classification:

H01L 27/088
H01L 29/66
H01L 21/8234

Abstract:

First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.

US Patent:

20190280105, Sep 12, 2019

Filed:

Mar 9, 2018

Appl. No.:

15/916323

Inventors:

- GRAND CAYMAN, KY
Hui Zang - Guilderland NY, US
Qun Gao - Clifton Park NY, US
Jerome Ciavatti - Mechanicville NY, US
Yi Qi - Niskayuna NY, US
Wei Hong - Clifton Park NY, US
Yongjun Shi - Clifton Park NY, US
Jae Gon Lee - Waterford NY, US
Chun Yu Wong - Ballston Lake NY, US

Assignee:

GLOBALFOUNDRIES INC. - GRAND CAYMAN

International Classification:

H01L 29/66
H01L 27/092
H01L 21/8238

Abstract:

Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

US Patent:

20190229183, Jul 25, 2019

Filed:

Jan 19, 2018

Appl. No.:

15/875132

Inventors:

- Grand Cayman, KY
Hui ZANG - Guilderland NY, US
Chun Yu WONG - Ballston Lake NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 29/06
H01L 27/088
H01L 21/762

Abstract:

A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

US Patent:

20160372425, Dec 22, 2016

Filed:

Aug 25, 2016

Appl. No.:

15/247513

Inventors:

- Grand Cayman KY, US
Sarasvathi Thangaraju - Malta NY, US
Chun Yu Wong - Ballston Lake NY, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman KY

International Classification:

H01L 23/00
H01L 21/48
H01L 25/07
H01L 23/498

Abstract:

Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.