Cliff Ching-Kong Lee

US Patent:

20060292739, Dec 28, 2006

Filed:

Jun 28, 2005

Appl. No.:

11/170558

Inventors:

Cliff Lee - Portland OR, US
Scott Gardiner - Beaverton OR, US
Jeffrey Krieger - Portland OR, US
Jen-Tai Hsu - El Dorado Hills CA, US
Fei Deng - Folsom CA, US

International Classification:

H01L 21/00
H01L 23/02

US Classification:

438106000, 257678000

Abstract:

A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers are adjacent. Other structures and methods are also described and claimed.

US Patent:

20080150122, Jun 26, 2008

Filed:

Dec 26, 2006

Appl. No.:

11/645820

Inventors:

Cliff Lee - Portland OR, US
David Browning - Beaverton OR, US
Brian Kelly - Hillsboro OR, US

International Classification:

H01L 23/48
H01L 21/4763

US Classification:

257698, 438618, 257E2301, 257E21495

Abstract:

Methods and apparatus to improve routing density through asymmetric array of vias are described. In one embodiment, a plurality of vias may be asymmetrically distributed relative to the distribution of a plurality of pads. Other embodiments are also described.

US Patent:

20120305303, Dec 6, 2012

Filed:

Jun 6, 2011

Appl. No.:

13/153608

Inventors:

Md Altaf Hossain - Portland OR, US
Cliff C. Lee - Portland OR, US
David W. Browning - Beaverton OR, US
Itai M. Pines - Beaverton OR, US
Brian P. Kelly - Hillsboro OR, US

International Classification:

H05K 1/16
H05K 1/11
H05K 1/00

US Classification:

174260, 174250, 174266

Abstract:

The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.

US Patent:

20220375869, Nov 24, 2022

Filed:

May 21, 2021

Appl. No.:

17/327199

Inventors:

- Redmond WA, US
Craig S. RANTA - Olympia WA, US
Cliff C. LEE - Bellevue WA, US
Douglas P. KELLEY - Sammamish WA, US
Matthew David TURNER - Carnation WA, US
David B. TUCKERMAN - Lafayette CA, US

International Classification:

H01L 23/532
H01L 39/22
H01L 27/092
H03K 19/195
H03K 19/0185
H01L 39/02

Abstract:

High temperature superconductor (HTS)-based interconnect systems comprising a cable including HTS-based interconnects are described. Each of the HTS-based interconnects includes a first portion extending from a first end towards an intermediate portion and a second portion extending from the intermediate portion to a second end. Each of the HTS-based interconnects includes a substrate layer formed in the first portion, in the intermediate portion, and in the second portion, a high temperature superconductor layer formed in at least a sub-portion of the first portion, in the intermediate portion, and in the second portion, and a metallic layer formed in the first portion and in at least a sub-portion of the intermediate portion. The HTS-based interconnect system includes a thermal load management system configured to maintain the intermediate portion of each of the HTS-based interconnects at a predetermined temperature in a range between a temperature of 60 kelvin and 92 kelvin.

US Patent:

20180005972, Jan 4, 2018

Filed:

Jul 1, 2016

Appl. No.:

15/201332

Inventors:

- Santa Clara CA, US
Cliff C. LEE - Portland OR, US

International Classification:

H01L 23/00
H01L 23/31
H01L 21/66

Abstract:

Techniques and mechanisms for determining an accessibility of circuit functionality via interface structures of a microelectronic device. In an embodiment, a packaged microelectronic device includes a substrate having interconnect structures formed therein. The interconnect structures variously couple one or more integrated circuit (IC) dies of the packaged microelectronic device to respective conductors (or “contact lands”) at a side of the substrate. Access to some functionality of the one or more IC dies via certain ones the contact lands—the access during an operational mode of the packaged microelectronic device—may be selectively disabled based on testing which evaluates performance characteristics of the packaged microelectronic device. In another embodiment, some of the contact lands are covered with an insulator material to prevent deposition of solder on such contact lands.

US Patent:

20140133075, May 15, 2014

Filed:

Jan 23, 2014

Appl. No.:

14/162002

Inventors:

Md Altaf Hossain - Portland OR, US
Cliff C. Lee - Portland OR, US
David W. Browning - Beaverton OR, US
Itai M. Pines - Beaverton OR, US
Brian P. Kelly - Hillsboro OR, US

International Classification:

H05K 1/11

US Classification:

36167902, 174261

Abstract:

The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.