Dae Il Kang

US Patent:

6870410, Mar 22, 2005

Filed:

Oct 15, 2002

Appl. No.:

10/272027

Inventors:

James Thomas Doyle - Nederland CO, US
Dae Woon Kang - Franklin MA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L007/00
H04L025/00

US Classification:

327149, 327152, 375371, 375373

Abstract:

An all digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes an up/down counter and a pulse width modulator to output a signal into a LC network that generates the supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal. The system supplies the optimum or minimum required voltage to insure that a critical path through a digital chip is met over process, voltage, and temperature (PVT) variations without the use of a band gap reference voltage source. A state machine is also used to counteract oscillations introduced by start up and load transients, thereby eliminating the need for a proportional integrator differentiator (PID).

US Patent:

7224199, May 29, 2007

Filed:

Nov 4, 2005

Appl. No.:

11/267415

Inventors:

Dae Woon Kang - Lafayette CO, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1/04

US Classification:

327291, 327298, 327299, 327175

Abstract:

A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal based on the at least one selected version of the second signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

US Patent:

7253598, Aug 7, 2007

Filed:

May 16, 2005

Appl. No.:

11/129969

Inventors:

James T. Doyle - Nederland CO, US
Dae Woon Kang - Boulder CO, US
Martin Dermody - Boulder CO, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G05F 1/16

US Classification:

323316, 323314, 327539

Abstract:

The performance of a bandgap reference circuit is improved by increasing the ΔVBE, and thereby correspondingly decreasing the input sensitivity of the error amplifier in the control loop. The ΔVBE can be increased by presenting stacked diode configurations at the amplifier inputs, by increasing the diode ratio presented at the amplifier inputs, and by providing a higher current in the CTAT leg than in the PTAT leg. The stacked diode configuration is achieved by producing isolated diodes with a triple well CMOS process. The stacked diode configuration and the triple well CMOS process also permit the input stage of the amplifier to use N-channel transistors operating in the threshold region.

US Patent:

7342425, Mar 11, 2008

Filed:

Sep 7, 2005

Appl. No.:

11/221187

Inventors:

Dae Woon Kang - Lafayette CO, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03B 19/00

US Classification:

327115, 327117, 377 48

Abstract:

A method and apparatus for dividing the frequency of an input clock signal by an odd integer is disclosed. The output of two asymmetrical clock dividers may be combined to produce a divided clock signal having a symmetrical waveform. Finite state machines may be used as asymmetrical clock dividers having desired duty cycles and relative turn-on and turn-off times to produce signals that combine to form a symmetrical divided clock signal. Alternatively, the output of an asymmetrical clock divider may be delayed by one input clock signal half-cycle and combined with the original asymmetrical signal to form a symmetrical divided clock signal.

US Patent:

7378893, May 27, 2008

Filed:

Dec 22, 2006

Appl. No.:

11/644476

Inventors:

Dae Woon Kang - Lafayette CO, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1/04

US Classification:

327291, 327298, 327299, 327175

Abstract:

A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

US Patent:

7436243, Oct 14, 2008

Filed:

Feb 24, 2005

Appl. No.:

11/065431

Inventors:

James T. Doyle - Nederland CO, US
Dae Woon Kang - Boulder CO, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G05F 3/16
G05F 1/10

US Classification:

327539, 323314, 327538, 327541

Abstract:

On-chip AC noise suppression is provided for a target circuit within an integrated circuit chip. A power supply line filter is provided in the power supply line that feeds the target circuit. The filter includes a polysilicon resistor formed over a charged substrate well, with a dielectric material interposed between the well and the resistor. This decreases capacitive coupling between the substrate and the resistor, thereby suppressing AC noise that is injected via the substrate. For an on-chip bandgap reference circuit, AC noise suppression can be achieved by providing matched AC impedances in the PTAT and inverse PTAT branches of the circuit. This technique exploits the common-mode rejection capability of the error amplifier within the bandgap reference circuit. Also, the inputs of the error amplifier can be capacitively coupled together to exploit the amplifier's common-mode rejection capability for the suppression of AC noise that is injected at the amplifier inputs.

US Patent:

7602166, Oct 13, 2009

Filed:

Oct 12, 2005

Appl. No.:

11/248893

Inventors:

Dae Woon Kang - Lafayette CO, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G05F 1/575

US Classification:

323283, 713322, 327262

Abstract:

A system and method is disclosed that provides a digital self-adjusting power supply for semiconductor digital circuits. The power supply provides a substantially constant minimum supply voltage with regard to process corner, junction temperature, external voltage source, load variation, and operating frequency. The system comprises a slack time detector, a voltage adjuster, and a digital pulse width modulation (PWM) modulator. The system supplies a minimum required voltage without the used of a band gap or reference voltage. A finite state machine is also used to minimize oscillations introduced by start-up, load transients, frequency changes, and the like, thereby eliminating the need for a proportional integrator differentiator (PID) circuit.

US Patent:

7676239, Mar 9, 2010

Filed:

Feb 24, 2005

Appl. No.:

11/065172

Inventors:

James T. Doyle - Nederland CO, US
Dae Woon Kang - Boulder CO, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H04B 7/00

US Classification:

455522, 455523, 4551143, 455136, 4551871

Abstract:

A method for operating a power controller in a wireless communication device is provided that includes generating a power controller output signal using an open loop polar modulation scheme. The power controller output signal is operable to control the power delivered to a high-band power amplifier and a low-band power amplifier. A band state is determined for the wireless communication device. The power controller output signal is provided to the high-band power amplifier when the band state is a high-band state and to the low-band power amplifier when the band state is a low-band state.