Dae Sik Kang

US Patent:

57421889, Apr 21, 1998

Filed:

Dec 10, 1996

Appl. No.:

8/763123

Inventors:

Leon Li-Feng Jiang - Gaithersburg MD
Kai Liu - Germantown MD
Dae Sun Kang - Germantown MD

Assignee:

Samsung Electronics., Ltd. - Suwon

International Classification:

H03K 1992
H03K 1716

US Classification:

327 99

Abstract:

A circuit for detecting timing errors and for selecting the correct clock edge for mid-point data sampling, includes a rising edge sampling device for sampling an input data signal at a rising edge of an input clock and generating a first interim data signal. A falling edge sampling device samples the input data signal at a falling edge of the input clock and generates a second interim data signal. An error signal generation devise, arranged in each of the rising edge and falling edge sampling devices, generates an error signal if designated setup time and hold time requirements are not met. The error signal is one of an error-rise or error-fall signal. A state machine receives the first and second interim signals and the error signal. The state machine automatically outputs the first interim data signal to a logic device if the error-fall signal is detected, and outputs the second interim data signal to the logic device if the error-rise signal is detected.

US Patent:

58450971, Dec 1, 1998

Filed:

Jun 3, 1996

Appl. No.:

8/657371

Inventors:

Ki B. Kang - Centreville VA
Dae S. Kang - Gaithersburg MD

Assignee:

Samsung Electronics Co., Ltd. - Suwon

International Classification:

G06F 13362

US Classification:

395297

Abstract:

A bus recovery system for multi-master bus system comprises a plurality of bus masters selectively interfacing with a system bus whereby access to the bus is controlled by a bus arbiter. A plurality of counters corresponding to each of the plurality of masters contains a pre-determined time value corresponding to the maximum time each of the plurality of masters may be granted access to bus. The arbiter releases ownership of the bus when the pre-determined time value in the counter has been exceeded by master currently accessing the bus. A register identifies which of the masters had access to the bus when the predetermined time value was exceeded.