Daniel C Chow

US Patent:

7123496, Oct 17, 2006

Filed:

May 10, 2004

Appl. No.:

10/841447

Inventors:

Jeffrey T. Nguyen - Portland OR, US
Daniel Chow - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 15/00

US Classification:

365 49, 36518513, 36523001

Abstract:

A L0 cache is provided that includes a plurality of memory cells, full swing signal bit lines coupled to the plurality of memory cells to output full swing data signals, small signal global bit lines coupled to the full swing signal bit lines to provide small signal data signals, and an alignment device to align signals on the small signal global bit lines.

US Patent:

8553472, Oct 8, 2013

Filed:

Dec 5, 2011

Appl. No.:

13/311340

Inventors:

Edward M. McCombs - Austin TX, US
Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/10

US Classification:

36518905, 365226, 365229, 365227, 36523008

Abstract:

A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.

US Patent:

8553481, Oct 8, 2013

Filed:

Aug 18, 2011

Appl. No.:

13/212450

Inventors:

Daniel C. Chow - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

365205, 365207, 36518905

Abstract:

A sense amplifier latch may be provided to controllably latch the output of a sense amplifier. The latch may open in response to assertion of a latch enable signal to receive data, and close in response to deassertion of the latch enable signal to capture and store the received data. Additionally, a multiplexer may be provided to select from among multiple sources of test data, such as scan data and bypass data. The multiplexer may produce a test data input to the sense amplifier latch that encodes a data value and a control value that causes the data value to be selected. Depending on the state of the test data input, the sense amplifier latch may output either a value received from the sense amplifier or a value encoded in the test data input.

US Patent:

8553482, Oct 8, 2013

Filed:

Aug 18, 2011

Appl. No.:

13/212490

Inventors:

Daniel C. Chow - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

365205, 36518902

Abstract:

A sense amplifier of a memory array may be provided to amplify data presented from storage cells of the memory array. Additionally, a sense amplifier latch may be provided to store data received from the sense amplifier. The sense amplifier may be enabled for operation by a sense amplifier enable signal that is distinct from a clock signal. Moreover, the latch enable signal of the sense amplifier latch may be controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier.

US Patent:

8570824, Oct 29, 2013

Filed:

Jan 24, 2012

Appl. No.:

13/356786

Inventors:

Edward M. McCombs - Austin TX, US
Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/02

US Classification:

365207, 365226, 36518911

Abstract:

A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

US Patent:

20130111130, May 2, 2013

Filed:

Nov 1, 2011

Appl. No.:

13/286351

Inventors:

Edward M. McCombs - Austin TX, US
Stephen C. Horne - Austin TX, US
Alexander E. Runas - Austin TX, US
Daniel C. Chow - Austin TX, US

International Classification:

G11C 5/14
G06F 12/08

US Classification:

711118, 365227, 711E12017

Abstract:

A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.

US Patent:

20140016392, Jan 16, 2014

Filed:

Sep 18, 2013

Appl. No.:

14/029989

Inventors:

Daniel C. Chow - Austin TX, US
Kenneth W. Jones - Austin TX, US
Alexander E. Runas - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 5/06

US Classification:

365 72

Abstract:

A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

US Patent:

59745355, Oct 26, 1999

Filed:

May 9, 1997

Appl. No.:

8/853009

Inventors:

Daniel Chen Chow - Hillsboro OR
Terence Matthew Potter - Austin TX
Paul Charles Rossbach - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

712215

Abstract:

A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.