Daniel Li

US Patent:

D579616, Oct 28, 2008

Filed:

Aug 15, 2007

Appl. No.:

29/283467

Inventors:

Daniel Li - Westminster CA, US

International Classification:

3205

US Classification:

D32 55, D7638

US Patent:

20040078712, Apr 22, 2004

Filed:

Sep 12, 2002

Appl. No.:

10/241789

Inventors:

Gurushankar Rajamani - Sunnyvale CA, US
Kent Dickey - Westford MA, US
Robert Shaw - Sunnyvale CA, US
Mark Shaw - Plano TX, US
Daniel Li - Saratoga CA, US

International Classification:

G06F011/00

US Classification:

714/043000

Abstract:

The present invention generally relates to the testing of computer systems by moving data from one location to another. More particularly, the present invention relates to a method for stressing the data paths of computer systems by increasing data traffic throughout the computer system without increasing checking overhead.

US Patent:

6412046, Jun 25, 2002

Filed:

May 1, 2000

Appl. No.:

09/562130

Inventors:

Debendra Das Sharma - Santa Clara CA
Kevin Hauck - Sunnyvale CA
Daniel F. Li - Saratoga CA

Assignee:

Hewlett Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711137, 711204, 712207, 714 32, 714 36

Abstract:

A method and apparatus automatically and easily verifies a cache line prefetch mechanism. The verification method includes a strict definition of which cache lines should be prefetched and which cache lines should not. The method also emphasizes unusual operating conditions. For example, by exercising boundary conditions, the method by stresses situations in which a microprocessor or chip is likely to produce errors. The method can verify prefetch without having to access or view any internal signals or buses inside the chip. The method can be adopted in any system-level verification methodology in simulation, emulation, or actual hardware. The method can be used in a system-level test set up along with a chip-level test set up without requiring knowledge of the internal state of the chip. In this case, checking is done at the chip boundary. The method is automated and performs strict checks on overprefetch, underprefetch, and the relative order in which fetch and prefetches must occur.

US Patent:

20190129934, May 2, 2019

Filed:

Oct 25, 2018

Appl. No.:

16/170314

Inventors:

- Princeton NJ, US
Daniel Li - Irvine CA, US

International Classification:

G06F 17/27
G06F 9/50
G06F 9/48
G06F 3/06

Abstract:

A method for performing question answer (QA) tasks that includes entering an input into an encoder portion of an adaptive memory network, wherein the encoder portion parses the input into entities of text for arrangement of memory banks. A bank controller of the adaptive memory network organizes the entities into progressively weighted banks within the arrangement of memory banks. The arrangement of memory banks may be arranged to have an initial memory bank having lowest relevance for lowest relevance entities being closest to the encoder, and a final memory bank having a highest relevance for highest relevance entities being closes to a decoder. The method may continue with inferring an answer for the question answer (QA) task with the decoder analyzing only the highest relevance entities in the final memory bank.