Daniel Li

US Patent:

D579616, Oct 28, 2008

Filed:

Aug 15, 2007

Appl. No.:

29/283467

Inventors:

Daniel Li - Westminster CA, US

International Classification:

3205

US Classification:

D32 55, D7638

US Patent:

7515478, Apr 7, 2009

Filed:

Aug 20, 2007

Appl. No.:

11/841468

Inventors:

Daniel D. Li - Highland CA, US
Steve X. Zhou - Boise ID, US

Assignee:

Nantronics Semiconductor, Inc. - San Ramon CA

International Classification:

G11C 16/04

US Classification:

36518526, 36518502, 36518505, 36518514, 36518518, 36518528, 36518529

Abstract:

The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance with the present invention comprises a program transistor with a program transistor source as a first program terminal; a select transistor with a select transistor gate as a select terminal and a select transistor drain as a second program terminal; and an erase transistor with an erase transistor source and an erase transistor drain connected as an erase terminal, wherein the erase transistor shares a floating gate with the program transistor and the drain program transistor is connected to the select transistor source. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided.

US Patent:

20190129934, May 2, 2019

Filed:

Oct 25, 2018

Appl. No.:

16/170314

Inventors:

- Princeton NJ, US
Daniel Li - Irvine CA, US

International Classification:

G06F 17/27
G06F 9/50
G06F 9/48
G06F 3/06

Abstract:

A method for performing question answer (QA) tasks that includes entering an input into an encoder portion of an adaptive memory network, wherein the encoder portion parses the input into entities of text for arrangement of memory banks. A bank controller of the adaptive memory network organizes the entities into progressively weighted banks within the arrangement of memory banks. The arrangement of memory banks may be arranged to have an initial memory bank having lowest relevance for lowest relevance entities being closest to the encoder, and a final memory bank having a highest relevance for highest relevance entities being closes to a decoder. The method may continue with inferring an answer for the question answer (QA) task with the decoder analyzing only the highest relevance entities in the final memory bank.