Daniel A Rosenthal

US Patent:

6661836, Dec 9, 2003

Filed:

Oct 17, 1999

Appl. No.:

09/419317

Inventors:

Wajih Dalal - Palo Alto CA
Daniel A. Rosenthal - Saratoga CA

Assignee:

NPTest, LLP - San Jose CA

International Classification:

H04B 1700

US Classification:

375226

Abstract:

A jitter measurement technique utilizing a high-bandwidth undersampling voltage measurement instrument is presented. A trigger is derived from the a signal having a repetitive signal pattern. The signal is compared with a threshold at a plurality of times relative to the trigger during multiple repetitions of the signal pattern to produce measurement samples indicative of signal level relative to the threshold. The measurement samples are used to determine the probability of signal edge states as a function of time for the multiple repetitions. The probability of signal edge states are used to determine an edge probability density as a function of time. A histogram of signal state transition times can be prepared from the edge probability density. Mean deviation of edge transitions of the signal can be estimates, and standard deviation of edge transitions of the signal can be estimated to give the root-mean-square (rms) jitter of the signal.

US Patent:

D664195, Jul 24, 2012

Filed:

Nov 3, 2011

Appl. No.:

29/405525

Inventors:

Daniel Rosenthal - Ross CA, US
Gerard Mullins - Hermosa Beach CA, US
Benito Aguilar - N Oswego IL, US

Assignee:

Kurtzman Carson Consultants, LLC - Novato CA

International Classification:

1901

US Classification:

D19 3, D19 1

US Patent:

D677329, Mar 5, 2013

Filed:

Jun 21, 2012

Appl. No.:

29/425336

Inventors:

Daniel Rosenthal - Ross CA, US
Gerard Mullins - Hermosa Beach CA, US
Benito Aguilar - N Oswego IL, US

Assignee:

Kurtzman Carson Consultants, LLC - Novato CA

International Classification:

1908

US Classification:

D19 3

US Patent:

20130113199, May 9, 2013

Filed:

Nov 3, 2011

Appl. No.:

13/288277

Inventors:

Daniel Rosenthal - Ross CA, US
Gerard Mullins - Hermosa Beach CA, US
Benito Aguilar - N Oswego IL, US

Assignee:

KURTZMAN CARSON CONSULTANTS, LLC - Novato CA

International Classification:

B42D 15/00

US Classification:

283 67, 283 58

Abstract:

A double postcard check mailer and a method of use therefore are described. The mailer is comprised of a check component and a payee data correction component detachably coupled to the check component. The mailer, when folded, has the dimensions of a double postcard. The mailer is sent to the payee of the check. The payee detaches the check component from the payee data correction component and cashes the check component. The payee further fills out the payee data correction component with updated information, such as a corrected address, and deposits the completed payee data correction component in the mail with postcard shipping postage. The original sender of the mailer receives the payee data correction component and updates the payee's information based on the data received in the completed payee data correction component.

US Patent:

59181982, Jun 29, 1999

Filed:

Oct 22, 1996

Appl. No.:

8/734994

Inventors:

Paolo Dalla Ricca - San Jose CA
Daniel Rosenthal - Saratoga CA

Assignee:

Schlumberger Technologies Inc. - San Jose CA

International Classification:

G01R 3128

US Classification:

702110

Abstract:

A method simulating the filtering of a current pulse in a series of pulses. The method includes receiving a series of n+1 consecutive pulse addresses, including a pulse address for the current pulse as the last in the series of n+1, each pulse address being in a range of m values; storing the n pulses addresses prior to the current pulse address; building a composite address from the current pulse address and the prior n pulse addresses and applying the composite address to read a pulse shape from a memory of at least m. sup. n+1 pulse shapes. Also, apparatus issuing high speed pulses of programmable length. The apparatus includes a field of programmable memory to store a pulse length; a pulse clock line carrying a pulse clock signal having a pulse frequency; a frequency multiplier connected to receive the pulse clock signal and the pulse length stored in the programmable memory field and producing a sample clock signal having a frequency equal to the pulse length times the pulse clock frequency; a pulse memory holding the samples for a pulse; a DAC coupled to the pulse memory and generating analog pulses from samples received from the pulse memory; and a signal path carrying the sample clock signal to set the sampling frequency of a DAC and to clock samples from the pulse memory to the DAC.

US Patent:

56465211, Jul 8, 1997

Filed:

Aug 1, 1995

Appl. No.:

8/510397

Inventors:

Daniel Rosenthal - Saratoga CA
Kannan Konath - Fremont CA
Robert Whyte - Ringwood, GB
Eric Norton - Cupertino CA
Stuart Robert Pearce - San Jose CA

Assignee:

Schlumberger Technologies, Inc. - San Jose CA

International Classification:

G01R 3128

US Classification:

3241581

Abstract:

Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT. This loop-back of the result of a test cycle within the analog channel to define the next test cycle speeds up the test process.

US Patent:

57481245, May 5, 1998

Filed:

Dec 9, 1996

Appl. No.:

8/762395

Inventors:

Daniel Rosenthal - Saratoga CA
Kannan Konath - Fremont CA
Robert Whyte - Ringwood, GB
Eric Norton - Cupertino CA
Stuart Robert Pearce - San Jose CA

Assignee:

Schlumberger Technologies Inc. - San Jose CA

International Classification:

H03M 110

US Classification:

341120

Abstract:

Mixed-signal tester architecture and methods are provided which minimize transfer of data, offer parallel data post-processing within the analog channels, and allow flexible synchronization. Multiple analog channels each have a source digital signal processor (DSP), a digital source sequencer, digital source instrumentation, analog source instrumentation, analog measure instrumentation, digital measure instrumentation, a digital pin multiplexer, a digital measure sequencer, DSP-addressable multi-bank capture memory, a capture digital signal processor, and an inter-DSP feedback path for communication between the source DSP and the capture DSP. Each analog channel can be arranged in a feedback loop through either its analog and/or digital instrumentation using the inter-DSP feedback path. DUT response is processed in the channel, the result is used to define parameters for a subsequent test cycle, and a signal corresponding to these parameters is generated and applied to the DUT. This loop-back of the result of a test cycle within the analog channel to define the next test cycle speeds up the test process.