David H Adler

US Patent:

6566885, May 20, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648109

Inventors:

Gustavo A. Pinto - Belmont CA
Brian C. Leslie - Cupertino CA
David L. Adler - San Jose CA
Akella V. S. Satya - Milpitas CA
Robert Thomas Long - Santa Cruz CA
David J. Walker - Sunol CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01R 3100

US Classification:

324501, 3562372, 250310

Abstract:

A sample is inspected. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

US Patent:

6524873, Feb 25, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648094

Inventors:

Akella V. S. Satya - Milpitas CA
David L. Adler - San Jose CA
Neil Richardson - Palo Alto CA
David J. Walker - Sunol CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01R 3126

US Classification:

438 18

Abstract:

Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.

US Patent:

6528818, Mar 4, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648380

Inventors:

Akella V. S. Satya - Milpitas CA
Gustavo A. Pinto - Belmont CA
David L. Adler - San Jose CA
Robert Thomas Long - Santa Cruz CA
Neil Richardson - Palo Alto CA
Kurt H. Weiner - San Jose CA
David J. Walker - Sunol CA
Lynda C. Mantalas - Campbell CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

H01L 2358

US Classification:

257 48, 257758

Abstract:

Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

US Patent:

6570154, May 27, 2003

Filed:

Jun 11, 2001

Appl. No.:

09/786137

Inventors:

Douglas K. Masnaghetti - San Jose CA
Stefano E. Concina - San Jose CA
Stanley S. Sun - Pleasanton CA
Waiman Ng - Los Gatos CA
David L. Adler - San Jose CA

Assignee:

KLA-Tencor Technologies Corporation - San Jose CA

International Classification:

H01J 37244

US Classification:

250310

Abstract:

A method and apparatus for generating an image of a specimen with a scanning electron microscope (SEM) is disclosed. The SEM ( ) has a source unit ( through ) for directing an electron beam ( ) substantially towards a portion of the specimen ( ), a detector ( ) for detecting particles ( ) that are emitted from the specimen ( ), and an image generator ( through ) for generating the image of the specimen ( ) from the emitted particles ( ). The image features are controlled by conditions under which the image is generated. The specimen is scanned under a first set of conditions ( ) to generate a first image during a first image phase ( ). The specimen is then scanned under a second set conditions ( ) during a setup phase ( ). The second set of conditions is selected to control charge on the specimen. The specimen is then scanned under the first set of conditions ( ) to generate a second image during a second image phase ( ).

US Patent:

6586733, Jul 1, 2003

Filed:

May 25, 2000

Appl. No.:

09/579867

Inventors:

Lee Veneklasen - Castro Valley CA
David L. Adler - San Jose CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01N 23225

US Classification:

250306, 250307, 250310

Abstract:

Disclosed is an apparatus for inspecting a sample. The apparatus includes a first electron beam generator arranged to direct a first electron beam having a first range of energy levels toward a first area of the sample and a second electron beam generator arranged to direct a second electron beam having a second range of energy levels toward a second area of the sample. The second area of the sample at least partly overlaps with the first area, and the second range of energy levels are different from the first range such that charge build up caused by the first electron beam is controlled. The apparatus further includes a detector arranged to detect secondary electrons originating from the sample as a result of the first and second electron beam interacting with the sample.

US Patent:

6610980, Aug 26, 2003

Filed:

May 11, 2001

Appl. No.:

09/854332

Inventors:

Lee Veneklasen - Castro Valley CA
David L. Adler - San Jose CA
Matthew Marcus - Santa Clara CA

Assignee:

KLA-Tencor Corporation - San Jose CA

International Classification:

G01N 2300

US Classification:

250310, 250302, 250305, 250306, 250251, 378 84, 378 85

Abstract:

A novel dual beam low energy electron microscope (LEEM) apparatus for inspecting semiconductor circuits or masks. Direct imaging records many pixels in parallel, offering higher inspection rates than prior art scanning methods. A low energy flood beam is superimposed with a second, higher energy flood beam. The use of two beams avoids charging effects upon insulating or partially insulating substrates. Under appropriate conditions, the net charging flux to each image element can be balanced on a pixel by pixel, as well as global basis. Either the low energy or the higher energy beam may be used to form an image of the surface. An electron optical apparatus and configuration for this dual beam LEEM is described.

US Patent:

6633174, Oct 14, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648093

Inventors:

Akella V. S. Satya - Milpitas CA
David L. Adler - San Jose CA
Neil Richardson - Palo Alto CA
Gustavo A. Pinto - Belmont CA
David J. Walker - Sunol CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01R 31305

US Classification:

324751, 324753, 3241581

Abstract:

Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.

US Patent:

6636064, Oct 21, 2003

Filed:

Aug 25, 2000

Appl. No.:

09/648092

Inventors:

Akella V. S. Satya - Milpitas CA
David L. Adler - San Jose CA
Neil Richardson - Palo Alto CA
Kurt H. Weiner - San Jose CA
David J. Walker - Sunol CA

Assignee:

KLA-Tencor - San Jose CA

International Classification:

G01R 3128

US Classification:

324763, 324751, 324765

Abstract:

Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element.