David H Chung

US Patent:

6696854, Feb 24, 2004

Filed:

Sep 17, 2001

Appl. No.:

09/956374

Inventors:

Afshin Momtaz - Irvine CA
Xin Wang - Irvine CA
Jun Cao - Irvine CA
Armond Hairapetian - Glendale CA
David Chung - Newport Beach CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 700

US Classification:

326 37, 326 40, 365221

Abstract:

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e. g. , the write clock, to be different than (e. g. , half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

US Patent:

6963221, Nov 8, 2005

Filed:

Dec 30, 2004

Appl. No.:

11/027193

Inventors:

Afshin Momtaz - Irvine CA, US
Xin Wang - Irvine CA, US
Jun Cao - Irvine CA, US
Armond Hairapetian - Glendale CA, US
David Chung - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

326 37, 326 40, 365221

Abstract:

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e. g. , the write clock, to be different than (e. g. , half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

US Patent:

7042271, May 9, 2006

Filed:

May 6, 2004

Appl. No.:

10/840524

Inventors:

David Kyong-Sik Chung - Irvine CA, US
Afshin Momtaz - Laguna Hills CA, US
Mario Caresosa - Rancho Santa Margarita CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 7/64

US Classification:

327341

Abstract:

A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.

US Patent:

7088797, Aug 8, 2006

Filed:

Sep 10, 2002

Appl. No.:

10/241140

Inventors:

Afshin Momtaz - Irvine CA, US
David Kyong-Sik Chung - Newport Beach CA, US
Pang-Cheng Hsu - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03D 3/24
H03L 7/06

US Classification:

375376, 327148, 327157

Abstract:

Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

US Patent:

7205792, Apr 17, 2007

Filed:

Dec 31, 2004

Appl. No.:

11/027848

Inventors:

Afshin Momtaz - Irvine CA, US
Xin Wang - Irvine CA, US
Jun Cao - Irvine CA, US
Armond Hairapetian - Glendale CA, US
David Chung - Newport Beach CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 8/04
G11C 7/00

US Classification:

326 46, 365240, 36518912, 365221

Abstract:

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e. g. , the write clock, to be different than (e. g. , half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

US Patent:

7839922, Nov 23, 2010

Filed:

May 18, 2004

Appl. No.:

10/847829

Inventors:

David Kyong-Sik Chung - Irvine CA, US
Afshin Momtaz - Laguna Hills CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03H 7/30

US Classification:

375233, 375232, 375229

Abstract:

An equalization circuit adjusts (e. g. , equalizes) an input signal according to the value of one or more adjustment signals (e. g. , equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

US Patent:

8283982, Oct 9, 2012

Filed:

Nov 3, 2010

Appl. No.:

12/939031

Inventors:

David Kyong-Sik Chung - Irvine CA, US
Afshin Momtaz - Laguna Hills CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03F 3/04

US Classification:

330304, 375233

Abstract:

An equalization circuit adjusts (e. g. , equalizes) an input signal according to the value of one or more adjustment signals (e. g. , equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

US Patent:

7994524, Aug 9, 2011

Filed:

Sep 12, 2007

Appl. No.:

11/900576

Inventors:

David Yaunien Chung - Los Angeles CA, US
Thomas Taoming Chung - Redondo Beach CA, US

International Classification:

H01L 33/48

US Classification:

257 90, 257 88, 257100, 257E33058, 257E2502, 257E25021

Abstract:

A vertical structured Light Emitting Diode (LED) array using wafer level bonding. The process bonds two or more LED arrays vertically to produce light mixing in a small footprint. The vertically bonded LED array contains through substrate vias and a plurality of metal posts coated with solder to form an internal cavity between the LED layers. This LED array structure is intrinsically hermetically sealed.