David N Chung

US Patent:

6696854, Feb 24, 2004

Filed:

Sep 17, 2001

Appl. No.:

09/956374

Inventors:

Afshin Momtaz - Irvine CA
Xin Wang - Irvine CA
Jun Cao - Irvine CA
Armond Hairapetian - Glendale CA
David Chung - Newport Beach CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 700

US Classification:

326 37, 326 40, 365221

Abstract:

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e. g. , the write clock, to be different than (e. g. , half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

US Patent:

6747518, Jun 8, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/335190

Inventors:

David Kyong-sik Chung - Newport Beach CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 07095

US Classification:

331 1A, 331DIG 2

Abstract:

A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.

US Patent:

6833763, Dec 21, 2004

Filed:

Apr 22, 2004

Appl. No.:

10/829755

Inventors:

David Kyong-sik Chung - Newport Beach CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 7095

US Classification:

331 1A, 331DIG 2

Abstract:

A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.

US Patent:

6940306, Sep 6, 2005

Filed:

Dec 31, 2003

Appl. No.:

10/750098

Inventors:

Afshin Momtaz - Laguna Hills CA, US
Xin Wang - Irvine CA, US
Jun Cao - Irvine CA, US
Armond Hairapetian - Glendale CA, US
David Chung - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

326 37, 326 40, 365221

Abstract:

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e. g. , the write clock, to be different than (e. g. , half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

US Patent:

6963220, Nov 8, 2005

Filed:

Dec 31, 2003

Appl. No.:

10/749965

Inventors:

Afshin Momtaz - Laguna Hills CA, US
Xin Wang - Irvine CA, US
Jun Cao - Irvine CA, US
Armond Hairapetian - Glendale CA, US
David Chung - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

326 37, 326 40, 365221

Abstract:

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e. g. , the write clock, to be different than (e. g. , half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

US Patent:

6963221, Nov 8, 2005

Filed:

Dec 30, 2004

Appl. No.:

11/027193

Inventors:

Afshin Momtaz - Irvine CA, US
Xin Wang - Irvine CA, US
Jun Cao - Irvine CA, US
Armond Hairapetian - Glendale CA, US
David Chung - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

326 37, 326 40, 365221

Abstract:

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e. g. , the write clock, to be different than (e. g. , half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

US Patent:

6982604, Jan 3, 2006

Filed:

Nov 2, 2004

Appl. No.:

10/979925

Inventors:

David Kyong-sik Chung - Newport Beach CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 7/095

US Classification:

331 1A, 331DIG 2

Abstract:

A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating the count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.

US Patent:

7042271, May 9, 2006

Filed:

May 6, 2004

Appl. No.:

10/840524

Inventors:

David Kyong-Sik Chung - Irvine CA, US
Afshin Momtaz - Laguna Hills CA, US
Mario Caresosa - Rancho Santa Margarita CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 7/64

US Classification:

327341

Abstract:

A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.