David R Doan

US Patent:

7126220, Oct 24, 2006

Filed:

Mar 17, 2003

Appl. No.:

10/390988

Inventors:

Syamal Kumar Lahiri - Milpitas CA, US
Frank Swiatowiec - San Jose CA, US
Fu Chiung Chong - Saratoga CA, US
Sammy Mok - Cupertino CA, US
Erh-Kong Chieh - Cupertino CA, US
Roman L. Milter - San Francisco CA, US
Joseph M. Haemer - San Jose CA, US
Chang-Ming Lin - San Jose CA, US
Yi-Hsing Chen - San Jose CA, US
David Thanh Doan - San Jose CA, US

Assignee:

NanoNexus, Inc. - San Jose CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257734, 257761, 257764

Abstract:

This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

US Patent:

7137830, Nov 21, 2006

Filed:

Mar 17, 2003

Appl. No.:

10/390994

Inventors:

Syamal Kumar Lahiri - Milpitas CA, US
Frank Swiatowiec - San Jose CA, US
Fu Chiung Chong - Saratoga CA, US
Sammy Mok - Cupertino CA, US
Erh-Kong Chieh - Cupertino CA, US
Roman L. Milter - San Francisco CA, US
Joseph M. Haemer - San Jose CA, US
Chang-Ming Lin - San Jose CA, US
Yi-Hsing Chen - San Jose CA, US
David Thanh Doan - San Jose CA, US

Assignee:

NanoNexus, Inc. - San Jose CA

International Classification:

H01R 12/00
H05K 1/00

US Classification:

439 81, 439 66, 439775, 438117, 438118, 257734

Abstract:

This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

US Patent:

7902004, Mar 8, 2011

Filed:

Oct 14, 2008

Appl. No.:

12/250780

Inventors:

Richard Weisfield - Los Altos CA, US
Kungang Zhou - San Jose CA, US
David Doan - San Jose CA, US

Assignee:

dpiX LLC - Palo Alto CA

International Classification:

H01L 21/00
H01L 21/84

US Classification:

438151, 438142, 438149, 257 72

Abstract:

A method is provided for fabricating an image sensor array in a manner that reduces the potential for defects resulting from electrostatic discharge events during fabrication of the image sensor array. The method includes: forming at least one pixel over a substrate, the pixel including a switching transistor and a photo-sensitive cell; and forming a dielectric interlayer over the pixel. A key step in the method of the present invention is depositing a first conductive layer over the dielectric interlayer. After the first conductive layer is formed, the image sensor array is well protected from ESD events because the first conductive layer spreads out any charge induced by tribo-electric charging events that may occur during subsequent fabrication processing steps, thereby reducing the potential for localized damage to the switching transistors upon the occurrence of ESD events.

US Patent:

20070144841, Jun 28, 2007

Filed:

Nov 2, 2006

Appl. No.:

11/556134

Inventors:

Fu Chong - Saratoga CA, US
Sammy Mok - Cupertino CA, US
Erh-Kong Chieh - Cupertino CA, US
Roman Milter - Alviso CA, US
Joseph Haemer - San Jose CA, US
David Doan - San Jose CA, US

International Classification:

F16F 9/32

US Classification:

188266700

Abstract:

This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

US Patent:

57908311, Aug 4, 1998

Filed:

Sep 18, 1996

Appl. No.:

8/715901

Inventors:

David H. Doan - San Jose CA

Assignee:

Opti Inc. - Milpitas CA

International Classification:

G06F 1314
G06F 1342

US Classification:

395500

Abstract:

A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#. The VL-bus controller does not receive BOFF# necessarily, but responds to LRDY# by asserting RDYRTN# onto the VL-bus, thereby signifying to all other VL-bus devices that the VL-bus cycle has ended and permitting them to restart their state machines in anticipation of a new VL-bus cycle. The host ignores RDYRTN# while, and only while, BOFF# is asserted.

US Patent:

59744952, Oct 26, 1999

Filed:

May 29, 1998

Appl. No.:

9/087229

Inventors:

David H. Doan - San Jose CA

Assignee:

OPTi Inc. - Milpitas CA

International Classification:

G06F 1340
G06F 1338

US Classification:

710127

Abstract:

A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#. The VL-bus controller does not receive BOFF# necessarily, but responds to LRDY# by asserting RDYRTN# onto the VL-bus, thereby signifying to all other VL-bus devices that the VL-bus cycle has ended and permitting them to restart their state machines in anticipation of a new VL-bus cycle. The host ignores RDYRTN# while, and only while, BOFF# is asserted.