David A Rolfe

US Patent:

55881521, Dec 24, 1996

Filed:

Aug 25, 1995

Appl. No.:

8/519859

Inventors:

Michael C. Dapp - Endwell NY
Thomas N. Barker - Vestal NY
James W. Dieffenderfer - Owego NY
Billy J. Knowles - Kingston NY
Donald M. Lesmeister - Vestal NY
Richard E. Nier - Apalachin NY
David B. Rolfe - West Hurley NY
Vincent J. Smoral - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1580

US Classification:

395800

Abstract:

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance.