David E Rowe

US Patent:

6509801, Jan 21, 2003

Filed:

Jun 29, 2001

Appl. No.:

09/895955

Inventors:

Binneg Y. Lao - Rancho Palos Verdes CA
David A. Rowe - Torrance CA
James R. Pulver - Torrance CA

Assignee:

Sierra Monolithics, Inc. - Redondo Beach CA

International Classification:

H03L 700

US Classification:

331 17, 331 1 A

Abstract:

Methods and apparatus for generating clock signals accurately locked to multi-gigabits-per-second data signals received over fiber optic channels are disclosed. The invention includes a phase detector for comparing a data signal and a clock signal, a one shot unit for detecting a data transition, an XOR, a filter, a main charge pump, a compensating charge pump for producing additive or compensating current, and a VCO for generating the clock signal. The phase detector includes multiple D-flip flops. The one shot unit includes a delay unit and an AND gate. The filter includes a resistor, a capacitor and a negative resistance amplifier. The main charge pump includes differential inputs, double outputs, cross-quading resistors, differential NPN input transistors, and a current source. The compensating charge pump includes differential NPN input transistors and a current source. In operation, when there is a data transition and if the clock signal and data signal are out of phase synchronization, then the compensating charge pump will enhance the operation of the main charge pump, and the VCO will speed up or slow down the clock signal depending on whether the clock signal is advanced or retarded in phase compared to the data signal.

US Patent:

6744325, Jun 1, 2004

Filed:

Apr 3, 2002

Appl. No.:

10/115400

Inventors:

David A. Rowe - Torrance CA

Assignee:

Sierra Monolithics, Inc. - Redondo Beach CA

International Classification:

H03B 2700

US Classification:

331 57, 331117 R, 331 56, 331 45, 331177 R, 331135, 375376

Abstract:

A quadrature ring oscillator for high clock-rate applications is disclosed. A quadrature LC ring oscillator may use two stages of LC oscillators and variable mixers to provide consistent oscillation even at high clock rates. One stage of the quadrature ring oscillator comprises a first resonating element having an input and an output, and a first variable summer having L and P inputs and an output, with its L input being connected to the output of the first resonating element. The output of the first variable summer is connected to the input of the first resonating element The first variable summer may generate its output at a first phase by combining the L and P inputs. A second stage of the LC ring oscillator comprises a second resonating element, which has an input and an output, with its output being connected to the P input of the first variable summer. An inverter is used to produce an inverted signal of the output of the first resonating element. This stage also comprises a second variable summer having L and P inputs and an output, with its output connected to the input of the second resonating element.

US Patent:

6803252, Oct 12, 2004

Filed:

Nov 21, 2001

Appl. No.:

09/990247

Inventors:

Binneg Y. Lao - Rancho Palos Verdes CA
William W. Chen - Westchester CA
David A. Rowe - Torrance CA
Inho Kim - Palo Alto CA

Assignee:

Sierra Monolithics, Inc. - Redondo Beach CA

International Classification:

H01L 2144

US Classification:

438106, 438122, 438123

Abstract:

Methods and apparatus for providing connection packages for high-speed integrated circuits (âICsâ) in optical, electronic, wired or wireless communications are disclosed. The connection package achieves dimensional transformation of signal routes from high-speed, high-density ICs input/output pads to the external terminals such as coaxial terminals and BGA balls, while maintaining constant characteristic impedance throughout the transmission lines. A package may include a substrate having microstrips for communicating signals between the IC pads and external terminals. A pair of differential microstrips can be positioned closer to each other near the IC pads and create capacitive coupling. Such coupled capacitance allows the width of the microstrips to be reduced. A portion of the coupled microstrips near the IC pads can be widened to increase the capacitance so that the overall transmission path can become an all-pass networkâfrom the IC pads, through the bonding wires, to the microstrips.

US Patent:

7155193, Dec 26, 2006

Filed:

Mar 22, 2004

Appl. No.:

10/806682

Inventors:

David A. Rowe - Torrance CA, US
Craig A. Hornbuckle - Torrance CA, US
Matthew D Pope - Rancho Palos Verdes CA, US

Assignee:

Sierra Monolithics, Inc. - Redondo Beach CA

International Classification:

H04B 1/38

US Classification:

455296, 4551142, 455266, 455295, 455306, 455307

Abstract:

A multi-channel filtering system for use with a transceiver includes a front-end multi-pole, multi-throw switch, a back-end multi-pole, multi-throw switch, and a plurality of filters. The front-end switch includes a receive pole, a transmit pole, and a plurality of switch throws. The back-end switch also includes a receive pole, a transmit pole, and a plurality of switch throws. Each of the plurality of filters has first and second ports, each first port coupled to one of the switch throws of the front-end switch, and each second port coupled to one of the switch throws of the back-end switch. Using this configuration, filters of differing bandwidths can be switched in during signal reception and/or transmission, thereby tailoring the communication rate to the particular conditions.

US Patent:

7231189, Jun 12, 2007

Filed:

Nov 9, 2006

Appl. No.:

11/594914

Inventors:

David A. Rowe - Torrance CA, US
Craig A. Hornbuckle - Torrance CA, US
Matthew D. Pope - Rancho Palos Verdes CA, US

Assignee:

Sierra Monolithics, Inc. - Redondo Beach CA

International Classification:

H04B 15/00
H04B 1/44
H04B 1/00

US Classification:

455 78, 455 633, 455306, 455307

Abstract:

A communication system includes a front-end multi-throw switch, a back-end multi-throw switch, multiple filters and a switch controller. The front-end multi-throw switch includes front-end throws and a front-end pole. The front-end pole is coupled to a receive channel or a transmit channel. The front-end pole is switchably coupled to one of the front-end throws. The back-end multi-throw switch includes back-end throws and a back-end pole. Each of the back-end throws is associated with a corresponding one of the front-end throws. The back-end pole is coupled to the receive channel or the transmit channel. The back-end pole is switchably coupled to one of the back-end throws. The one of the back-end throws corresponds to the one of the front-end throws. The filters are interposed between the front-end multi-throw switch and the back-end multi-throw switch. Each of the filters has a first port coupled to one of the front-end throws and a second port coupled to one of the back-end throws.

US Patent:

7286572, Oct 23, 2007

Filed:

Jan 10, 2003

Appl. No.:

10/338972

Inventors:

Craig A. Hornbuckle - Torrance CA, US
David A. Rowe - Torrance CA, US
Samuel A. Steidl - Torrance CA, US
Inho Kim - Palo Alto CA, US

Assignee:

Sierra Monolithics, Inc. - Redondo Beach CA

International Classification:

H04J 3/02

US Classification:

370537, 370907

Abstract:

An integrated circuit includes a serdes framer interface (SFI) circuit for receiving a first set of data channels and a reference channel, generating first logic levels for the first set of data channels, and realigning the first set of data channels relative to a reference channel. The integrated circuit further includes a multiplexing circuit for receiving a second set of data channels and for merging the second set of data channels into one or more data channels. The second set of data channels is generated based on the first set of data channels. A data rate of the one or more data channels is higher than a data rate of the second set of data channels.

US Patent:

7826542, Nov 2, 2010

Filed:

Dec 26, 2006

Appl. No.:

11/644949

Inventors:

David A. Rowe - Torrance CA, US

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H04K 1/10
H04B 1/10

US Classification:

375260, 375350

Abstract:

A channelization filter communication system comprises: a channelization filtering system, a calibration unit, amplifiers, communication channel frequency converters and a baseband processor. The channelization filtering system includes a selector input configured to receive a communication channel filter selector signal and selectable communication channel filter elements. The selectable communication channel filter elements include one or more resistors formed of a first resistor type and one or more capacitors formed of a first capacitor type. The calibration unit includes a calibration signal generator configured to provide a calibration signal and a frequency measurement unit. The calibration signal generator includes one or more resistors formed of the same first resistor type and one or more capacitors formed of the same first capacitor type. The frequency measurement unit includes a first input configured to receive the calibration signal and an output configured to provide information representing the frequency of the calibration signal.

US Patent:

7848367, Dec 7, 2010

Filed:

Aug 30, 2007

Appl. No.:

11/896162

Inventors:

Craig A. Hornbuckle - Torrance CA, US
David A. Rowe - Torrance CA, US
Samuel A. Steidl - Torrance CA, US
Inho Kim - Palo Alto CA, US

Assignee:

Sierra Monolithics, Inc. - Redondo Beach CA

International Classification:

H04J 3/02

US Classification:

370537, 370907

Abstract:

High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.