David C Sheppard

US Patent:

48993425, Feb 6, 1990

Filed:

Feb 1, 1988

Appl. No.:

7/150814

Inventors:

David Potter - Acton MA
Laurence N. Provost - Arlington MA
John M. Baron - Grafton MA
David Stefanovic - Allston MA
Eric D. Sharakan - Brighton MA
David A. Sheppard - Cambridge MA
Marshall A. Isman - Newton MA

Assignee:

Thinking Machines Corporation - Cambridge MA

International Classification:

G06F 1110

US Classification:

371 101

Abstract:

A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retrieved from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced. Preferably, the sequence of correction bits is generated by the same ECC circuit which generates the error correction codes; and the sequence of correction bits is connected to the spare memory unit, a repaired unit or a replacement unit through an array of multiplexers.

US Patent:

56445792, Jul 1, 1997

Filed:

Dec 22, 1994

Appl. No.:

8/363424

Inventors:

David William Sheppard - Mission Viejo CA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

A maintenance interface system for testing the Logic states of circuitry in digital modules provides for selecting a snake data path and using its control to Write into or to Read out in a forward sequence or selectively in a reverse sequence.