David J Warren

US Patent:

6414682, Jul 2, 2002

Filed:

Dec 28, 1998

Appl. No.:

09/220596

Inventors:

David S. Warren - Mountain View CA
David L. Dignam - Belmont CA

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 1500

US Classification:

345428

Abstract:

The present invention provides a system, apparatus and method for filtering an image that produces output images having high resolution without visual discontinuity across a wide range of resize ratios. The invention includes a linear filter for source images requiring low magnification and a higher order filter for source images requiring high magnification. In the transition region an interpolation is performed between the linear and higher order filters to provide a smooth transition in filtering and magnification to produce an output image.

US Patent:

8643417, Feb 4, 2014

Filed:

Jul 11, 2012

Appl. No.:

13/546540

Inventors:

Diarmuid P. Ross - Mountain View CA, US
Douglas C. Lee - Cupertino CA, US
David S. Warren - Campbell CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H03L 7/00

US Classification:

327161

Abstract:

A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.

US Patent:

20100245401, Sep 30, 2010

Filed:

Sep 26, 2008

Appl. No.:

12/680444

Inventors:

Euan C. Smith - Cambridgeshire, GB
David S. Warren - Sunnyvale CA, US
Richard Alan Page - Mountain View CA, US
Stefan Wurster - Livermore CA, US
Barry Thompson - Menlo Park CA, US

Assignee:

CAMBRIDGE DISPLAY TECHNOLOGY LIMITED - Cambridgeshire

International Classification:

G09G 5/00

US Classification:

345690, 345204, 345 76

Abstract:

A method of driving an electro-optic display comprising providing a current source, digitally modulating the current source and generating a modulated digital signal, and converting the modulated digital signal into an effective analog drive signal so that the display pixels receive an effective analog drive current, wherein the internal capacitance of the electro-optic display smooths the digitally modulated signal and generates the effective analog drive signal.

US Patent:

20130060363, Mar 7, 2013

Filed:

Sep 2, 2011

Appl. No.:

13/224439

Inventors:

David S. Warren - Campbell CA, US

International Classification:

G06F 17/00

US Classification:

700 94

Abstract:

An apparatus includes a first unit and a second functional units operating in a master-slave configuration. The first and second functional units operate as a master and slave, respectively. The first functional unit conveys clock and framing signals to the second functional unit. The second functional unit includes a buffer and a multiplexer having inputs coupled to the buffer. Digital audio data may be prefetched into the buffer. When a controller of the second functional unit detects assertion of the framing signal, it may cause a change of state to a selection signal provided to the multiplexer. Responsive thereto, the multiplexer selects an input coupled to receive, from the buffer, a next frame of data to be transmitted. A first bit of the frame is transmitted to the first functional unit on the same clock cycle in which assertion of the framing signal was detected.

US Patent:

20130259483, Oct 3, 2013

Filed:

Oct 27, 2010

Appl. No.:

13/881004

Inventors:

Moray McLaren - Bristol, GB
Nathan Lorenzo Binkert - Redwood City CA, US
David A. Warren - El Dorado Hills CA, US
Michael Renne Ty Tan - Menlo Park CA, US

Assignee:

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. - Houston TX

International Classification:

H04J 14/02

US Classification:

398 79

Abstract:

This disclosure is directed to optical-to-electrical receiver and transceiver integrated circuits that can be used to send and receive multiple optical signal data streams using at least one optical bus. In one aspect, a fan-in integrated circuit of a node includes an arbiter/multiplexer, and at least one receiver. Each receiver is electronically connected to the arbiter/multiplexer. Each receiver receives at least one optical signal over an optical broadcast bus and converts the optical signals into a data stream encoded in electronic signals. The arbiter/multiplexer selects one receiver at a time to send an electronic signal to the arbiter/multiplexer and outputs the electronic signal to the node for processing.

US Patent:

63043009, Oct 16, 2001

Filed:

Nov 12, 1998

Appl. No.:

9/191456

Inventors:

David S. Warren - Mountain View CA
Andrew D. Bowen - San Jose CA
David L. Dignam - Belmont CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

H04N 5202

US Classification:

348674

Abstract:

The present invention provides a method, a device, and a system for performing gamma correction on a set of pixel data based on a gamma correction curve table. The gamma correction curve table includes a specified total number of intensity levels associated with gamma corrected pixel values with one intensity level per pixel value. The method includes partitioning the gamma correction curve table into N segments such that each of the N segments is associated with a set of intensity levels from the specified total number of intensity levels. A plurality of intensity levels is selected for each of the N segments such that significant banding effects are not visible to the human eye between an adjacent pair of the selected intensity levels. The gamma corrected pixel values are stored for each of the N segments such that each of the plurality of selected intensity levels functions as an index to the associated gamma corrected pixel values. Gamma correction is performed on the set of pixel data by accessing a stored pixel value in one of the N segments in response to the pixel data to generate gamma corrected pixel data.

US Patent:

61476951, Nov 14, 2000

Filed:

Aug 26, 1998

Appl. No.:

9/140396

Inventors:

Andrew Bowen - San Jose CA
Gregory M. Eitzmann - Palo Alto CA
David Warren - Mountain View CA
Dawn Maxon - Belmont CA
Michael T. Jones - San Jose CA
David L. Dignam - Belmont CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1516
G06T 340

US Classification:

345503

Abstract:

An operation for combining multiple video streams permits combining any number of overlay images and base images regardless of processes performed upon one or more of the images. Specifically, where the base images are dynamically sized and resized to provide a constant frame rate (despite varying frame complexity), the process similarly treats overlay images and even other base images. In the dynamic sizing process, a rendering time is compared to high and low water marks. During dynamic resizing, two double buffering operations and a synchronization operation are performed. After dynamic sizing and resizing, the resulting resized images are combined together, regardless of the frame rate of the individual images. Consequently, multiple video streams at varying frame rates are combined at a constant frame rate.

US Patent:

20190377705, Dec 12, 2019

Filed:

Aug 21, 2019

Appl. No.:

16/547487

Inventors:

- Mountain View CA, US
Jason Redgrave - Mountain View CA, US
Neeti Desai - Sunnyvale CA, US
David Warren - Campbell CA, US

International Classification:

G06F 15/78
G06T 1/20

Abstract:

An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.