David C Wu

Address:

15 Danford Ct, Redwood City, CA 94062

Phone:

(650)8141830

VIN:

WBSNB935X7CX07314

Make:

BMW

Model:

M5

Year:

2007

US Patent:

6351013, Feb 26, 2002

Filed:

Jul 13, 1999

Appl. No.:

09/352339

Inventors:

Scott Luning - San Francisco CA
David Wu - San Jose CA
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 31062

US Classification:

257368, 257372, 257900, 257369, 438595

Abstract:

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

US Patent:

6683467, Jan 27, 2004

Filed:

Sep 29, 2000

Appl. No.:

09/672689

Inventors:

Ali Keshavarzi - Portland OR
David M. Wu - Austin TX
Yibin Ye - Hillsboro OR
Vivek K. De - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3102

US Classification:

324760, 3241581

Abstract:

A method and device are provided for stress testing a chip. The chip may be partitioned into at least a first block and a second block. Burn-in stress testing may be performed on electronic devices within the first block without simultaneously performing burn-in stress testing on electronic devices within the second block. A burn-in stress testing device may perform the burn-in testing. A control device may be coupled to the burn-in stress testing device to enable burn-in stress testing on electronic devices within at least the first block of the chip without simultaneously enabling burn-in stress testing on the second block of the chip.

US Patent:

6727558, Apr 27, 2004

Filed:

Feb 15, 2001

Appl. No.:

09/784790

Inventors:

Michael P. Duane - Santa Clara CA
David D. Wu - Austin TX
Massud Aminpur - Dresden, DE
Scott D. Luning - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21425

US Classification:

257377, 257374, 257510, 257382

Abstract:

A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

US Patent:

6775722, Aug 10, 2004

Filed:

Jul 5, 2001

Appl. No.:

09/899426

Inventors:

David Wu - Sunnyvale CA
Jerry Kuo - San Jose CA

Assignee:

Zarlink Semiconductor V. N. Inc. - Irvine CA

International Classification:

G06F 300

US Classification:

710 53, 710 52, 710 5, 710 6, 710 20, 710 21, 710 29, 710 54

Abstract:

An architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.

US Patent:

6784101, Aug 31, 2004

Filed:

May 16, 2002

Appl. No.:

10/146029

Inventors:

Bin Yu - Cupertino CA 95014
David Wu - Austin TX 78759

International Classification:

H01L 2144

US Classification:

438666, 438197, 438198, 438199

Abstract:

A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.

US Patent:

7087509, Aug 8, 2006

Filed:

Sep 28, 2000

Appl. No.:

09/676197

Inventors:

William R. Roche - Beaverton OR, US
David Donggang Wu - Austin TX, US
Massud Aminpur - Dresden, DE
Scott D. Luning - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/3205
H01L 21/4763

US Classification:

438595, 438197, 438585, 438669, 438659, 438714

Abstract:

The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.

US Patent:

7650416, Jan 19, 2010

Filed:

Aug 12, 2003

Appl. No.:

10/640459

Inventors:

David Tze-Si Wu - Fremont CA, US
Steven McCanne - Berkeley CA, US

Assignee:

Riverbed Technology - San Francisco CA

International Classification:

G06F 15/16
G06F 15/173

US Classification:

709228, 709227, 709229, 709238, 709239

Abstract:

In a network supporting transactions between clients and servers over a network path having operating characteristics to overcome, data is transported to overcome the operating characteristics using user affinities and dynamic user location information to selectively preload data, or representations, signatures, segments, etc. of data, in order to overcome the one or more operating characteristic. Examples of operating characteristics to overcome include bandwidth limitations, errors and latency. The dynamic location information can be stored in data structures accessible by agents of a data server and the data structures are populated based on user activities with respect to proxies associated with user locations, or the dynamic location information can be obtained implicitly as proxies maintain connections after termination by clients and the use of those maintained connections for preloading of data for the users associated with those clients. The data being preloaded can be protocol-specific data or protocol-independent data.

US Patent:

7853699, Dec 14, 2010

Filed:

Nov 14, 2005

Appl. No.:

11/273861

Inventors:

David Tze-Si Wu - Fremont CA, US
Vivasvat Keswani - Fremont CA, US
Case Larsen - Union City CA, US

Assignee:

Riverbed Technology, Inc. - San Francisco CA

International Classification:

G06F 15/16

US Classification:

709227, 709217

Abstract:

Network proxies reduce server latency in response to series of requests from client applications. Network proxies intercept messages clients and a server. Intercepted client requests are compared with rules. When client requests match a rule, additional request messages are forwarded to the server on behalf of a client application. In response to the additional request messages, the server provides corresponding response messages. A network proxy intercepts and caches the response messages. Subsequent client requests are intercepted by the network application proxy and compared with the cached messages. If a cached response message corresponds with a client request message, the response message is returned to the client application immediately instead of re-requesting the same information from the server. A server-side network proxy can compare client requests with the rules and send additional request messages. The corresponding response messages can be forwarded to a client-side network proxy for caching.