Deborah R Riley

US Patent:

20140011340, Jan 9, 2014

Filed:

Jul 5, 2012

Appl. No.:

13/541957

Inventors:

Seung-Chul Song - San Diego CA, US
Amitabh Jain - Allen TX, US
Deborah J. Riley - Murphy TX, US

International Classification:

H01L 21/20

US Classification:

438478, 257E2109

Abstract:

A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.