Deborah A Riley

US Patent:

20160284691, Sep 29, 2016

Filed:

Jun 3, 2016

Appl. No.:

15/172559

Inventors:

- Dallas TX, US
Terry J. BORDELON - Niskayuna NY, US
Deborah J. RILEY - Murphy TX, US

International Classification:

H01L 27/06
H01L 29/10
H01L 29/78
H01L 29/165
H01L 29/737
H01L 29/417
H01L 23/535

Abstract:

An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.