Donald J Cook

US Patent:

43553982, Oct 19, 1982

Filed:

Dec 17, 1980

Appl. No.:

6/217339

Inventors:

Donald M. Cook - Poway CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

H04L 702

US Classification:

375110

Abstract:

This invention relates to a real time clock recovery circuit. The clock recovery circuit requires three inputs, a bit serial data received input (BSD), a quarter bit delayed (QBT) and a three quarter bit delayed (TQBT) signal. The three inputs are derived from a single raw input that becomes the received input (BSD) signal. QBT and TQBT are delay line versions of the BSD signal. The three inputs (BSD, QBT and TQBT, and the complement of these signals) are ANDed together to detect low frequencies. The generated signal indicative of the low frequency, QBT and TQBT generate a recovered clock by state sequencing of an R-S latch. The type of bit serial data stream which may be inputted to the circuit of the present invention is double frequency encoded data streams, including Manchester or diphase encoded.

US Patent:

43922260, Jul 5, 1983

Filed:

Sep 28, 1981

Appl. No.:

6/306118

Inventors:

Donald M. Cook - Poway CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1100

US Classification:

371 61

Abstract:

This invention relates to an error detection circuit for detecting errors in a recovered clock signal from a self-clocking digital data signal. A first flip-flop is alternately set and reset by the recovered clock signal and by a clock source of supposedly equal frequency, respectively. The output of the first flip-flop is sensed by a second flip-flop at the end of a predetermined time period, as determined by the clock source, for determining that a transition in the recovered clock source occurred within the predetermined time period. If no transition occurred within the predetermined time period, the second flip-flop outputs an error signal.