Edmond Cheng

US Patent:

20070096760, May 3, 2007

Filed:

Oct 31, 2005

Appl. No.:

11/263089

Inventors:

Edmond Cheng - Cedar Park TX, US
Addi Mistry - Austin TX, US
David Patten - Austin TX, US

International Classification:

G01R 31/26

US Classification:

324765000

Abstract:

A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections is provided. The method may include providing a device socket for connecting the set of top-side connections and the set of bottom-side connections to a tester. The method may further include providing a device hood for connecting the set of top-side connections to a respective first end of each of a plurality of interconnects in the device hood, wherein a second end of each of the plurality of interconnects in the device hood connects the set of top-side connections to the device socket. The method may further include testing the semiconductor structure using the tester. The semiconductor structure may include at least one integrated circuit to be tested.