Eric Rowe

US Patent:

6516373, Feb 4, 2003

Filed:

Jun 18, 1999

Appl. No.:

09/335954

Inventors:

Gerald Talbot - Concord MA
Hanwoo Cho - Concord MA
Eric Rowe - Natick MA

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

G06F 1300

US Classification:

710301, 710104

Abstract:

A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. In this manner, a multiple of processor modules of completely different processor architectures can share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or simply allowing the same motherboard to be employed in two different products of different processor architectures.

US Patent:

6772328, Aug 3, 2004

Filed:

Jun 18, 1999

Appl. No.:

09/335939

Inventors:

Gerald Talbot - Concord MA
Hanwoo Cho - Concord MA
Eric Rowe - Natick MA

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

G06F 15177

US Classification:

713 1, 713 2, 710 8

Abstract:

In a common processor module/motherboard interface, an interface protocol is defined such that a replacement processor module can be recognized by a common motherboard and such that a common processor module can be compatible with multiple motherboards. A module information field stored on a processor module includes status information pertaining to the processor module. When the processor module is coupled to a motherboard, the motherboard downloads the module information field and generates initialization commands for the processor module based on the retrieved module information field. The commands are transferred to the processor module for initialization of the processor.

US Patent:

57670994, Jun 16, 1998

Filed:

Oct 20, 1995

Appl. No.:

8/546086

Inventors:

David J. Harris - Lexington MA
Edward R. Lee - Quincy MA
Craig S. Siegel - Woburn MA
Eric A. Rowe - Malden MA
Shirley C. Hubbard - Belmont MA

Assignee:

Genzyme Corporation - Cambridge MA

International Classification:

A61K 3170
A61K 1728
A61K 3156
A61K 4800
B61F 1728

US Classification:

514 44

Abstract:

Novel cationic amphiphiles are provided that facilitate transport of biologically active (therapeutic) molecules into cells. The amphiphiles contain lipophilic groups derived from steroids, from mono or dialkylamines, or from alkyl or acyl groups; and cationic groups, protonatable at physiological pH, derived from amines, alkylamines or polyalkylamines. There are provided also therapeutic compositions prepared typically by contacting a dispersion of one or more cationic amphiphiles with the therapeutic molecules. Therapeutic molecules that can be delivered into cells according to the practice of the invention include DNA, RNA, and polypeptides. Representative uses of the therapeutic compositions of the invention include providing gene therapy, and delivery of antisense polynucleotides or biologically active polypeptides to cells. With respect to therapeutic compositions for gene therapy, the DNA is provided typically in the form of a plasmid for complexing with the cationic amphiphile. Novel and highly effective plasmid constructs are also disclosed, including those that are particularly effective at providing gene therapy for clinical conditions complicated by inflammation.

US Patent:

59876220, Nov 16, 1999

Filed:

Dec 10, 1993

Appl. No.:

8/166345

Inventors:

Susan Lo Verso - Southborough MA
Eric Sharakan - Brookline MA
Eric L. Rowe - Natick MA
Roger Lee - Monrovia CA

Assignee:

TM Patents, LP - Boston MA

International Classification:

G06F 1100

US Classification:

714 6

Abstract:

A parallel computer system comprising a plurality of processing elements and an input/output system interconnected by a communications network. The input/output system includes a plurality of input/output devices connected to the communications network for receiving messages from, and transmitting messages to, the processing elements over the communications network. The processing element during the storage operation generates a series of messages for transmission over the communications network to successive input/output devices. Each message includes a data item from one of a series of storage locations. The processing element generates for each stripe of a selected number of data items a check value for transmission in a message to another of the input/output devices. During a reconstruction operation, the processing element receives the data items and the check values from at least some of the input/output devices and performs a reconstruction operation in connection with each check value and a stripe of data values for which the check value was generated during the storage operation thereby to reconstruct data items stored in at least one other of the input/output devices.