Eugene J Phillips

US Patent:

40123073, Mar 15, 1977

Filed:

Dec 5, 1975

Appl. No.:

5/638008

Inventors:

Eugene Phillips - Diamond Bar CA

Assignee:

General Dynamics Corporation - Pomona CA

International Classification:

C23C 1500

US Classification:

204192E

Abstract:

A method for conditioning drilled holes in multilayer printed wiring boards by removing layers of smeared plastic and adhesive prior to metal plating through the holes for interconnecting conductive layers of the boards includes baking the drilled boards and etching the boards within a plasma reactor chamber, with a predetermined gas pressure, the plasma being created by an RF generator. At the end of a predetermined time period, the RF generator is deactivated and atmospheric air is admitted to the reactor chamber. The reactor chamber is then purged of gases and the printed wiring boards are removed.

US Patent:

45685622, Feb 4, 1986

Filed:

Nov 28, 1984

Appl. No.:

6/675792

Inventors:

Eugene Phillips - Diamond Bar CA

Assignee:

General Dynamics, Pomona Division - Pomona CA

International Classification:

B05D 306

US Classification:

427 40

Abstract:

A method for electroless overplating of a conductive metal on printed wiring circuitry components mounted upon a plastic substrate which eliminates deposit metal overgrowth upon the plastic substrate and plastic bonding materials. The substrate and printed wiring are treated by exposure to a tetrafluoromethane plasma environment to chemically passivate, or neutralize, the plastic or adhesive substrate surface areas prior to electroless plating of the printed circuitry elements, thus preventing the establishment of catalyzing ions on the plastic or adhesive surfaces and subsequent lay down of the deposited metal thereon.

US Patent:

41417828, Feb 27, 1979

Filed:

Jan 30, 1978

Appl. No.:

5/873453

Inventors:

William P. Dugan - Pomona CA
Eugene Phillips - Diamond Bar CA

Assignee:

General Dynamics Corporation - Pomona CA

International Classification:

C23F 102
B29C 1708
H01L 21306
H01L 21312

US Classification:

156643

Abstract:

Carriers forming strips for semiconductor integrated circuit chips. The carrier consists basically of a flexible tape, such as a polyimide. A conductive sheet, such as a copper sheet, is initially prepared to form a lead circuit on one surface and a bump circuit on the other. This metal sheet may be gold plated. Subsequently, a layer of polyimide is applied to the lead circuit side and both the polyimide sheet and the opposite bump circuit are covered with a metal sheet, such as copper. A photoresist layer is put over the copper and is suitably illuminated and developed to provide apertures through which the copper can be etched to expose the polyimide sheet. This takes place over the windows or openings adjacent the bumps for the application of a heat ram as well as for the sprocket holes used for precisely aligning the carrier with the to-be-associated semiconductor chips. Finally, openings may also be provided to separate adjacent carrier strips from each other. The exposed polyimide layer is now removed by chemical milling.