Sandra G. Malhotra - San Jose CA, US Hanhong Chen - Milpitas CA, US Wim Y. Deweerd - San Jose CA, US Edward L. Haywood - San Jose CA, US Hiroyuki Ode - Higashihiroshima, JP Gerald Richardson - San Jose CA, US
Assignee:
Intermolecular, Inc. - San Jose CA Elpida Memory, Inc. - Tokyo
International Classification:
H01L 21/4763
US Classification:
438624, 438612, 438622, 438625, 438653, 438694
Abstract:
A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.
Hanhong Chen - Milpitas CA, US Wim Y. Deweerd - San Jose CA, US Edward L. Haywood - San Jose CA, US Hiroyuki Ode - Higashihiroshima, JP Gerald Richardson - San Jose CA, US
Assignee:
INTERMOLECULAR, INC. - San Jose CA
International Classification:
H01L 29/92
US Classification:
257532
Abstract:
A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.
Low Energy Vortex Liquid Treatment Systems And Methods
A method comprises steps for (a) providing a liquid in a container; (b) flowing a gas to a volume within the liquid, wherein the volume is at least partially submerged in the liquid; and (c) repeatedly increasing and decreasing the volume, wherein the cycles of increasing and decreasing generates a pulsed aerated flow, wherein at least one of the pulsed aerated flow is released within the container and the pulsed aerated flow is released outside the container.
Intermolecular - San Jose, Ca since Sep 2012
Equipment Support Supervisor
Intermolecular - San Jose, ca Jul 2011 - Sep 2012
Process Engineer
Intermolecular May 2008 - Aug 2011
Sr. Process Associate
Novellus Systems Sep 2000 - Mar 2007
Equipment Engineer II
United States Navy Sep 1996 - Sep 2000
Aviation Electronics Technician
Skills:
Semiconductors Troubleshooting PVD CVD Semiconductor Industry Metrology Thin Films Process Integration ALD SPC Semiconductor Process Silicon Design of Experiments