Gregory Patrick Wilson

Address:

841 Marias Dr, Saint Louis, MO 63137

VIN:

4T1BE46K97U684801

Make:

TOYOTA

Model:

CAMRY

Year:

2007

US Patent:

6537655, Mar 25, 2003

Filed:

May 16, 2001

Appl. No.:

09/859094

Inventors:

Gregory M. Wilson - Chesterfield MO
Jon A. Rossi - Chesterfield MO
Charles C. Yang - St. Peters MO

Assignee:

MEMC Electronic Materials, Inc. - St. Peters MO

International Classification:

C30B 2906

US Classification:

4283105, 428450, 117 2, 117 3, 117 89, 117935

Abstract:

This invention is directed to a novel a single crystal silicon wafer. In one embodiment, this wafer comprises: (a) two major generally parallel surfaces (i. e. , the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer. This wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein (a) the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer, (b) the crystal lattice vacancies have a concentration profile in which the peak density of the crystal lattice vacancies is at or near the central plane, and (c) the concentration of crystal lattice vacancies generally decreases from the position of peak density toward the front surface of the wafer. In addition, the front surface of the wafer has an epitaxial layer deposited thereon. This epitaxial layer has a thickness of from about 0.

US Patent:

6743495, Jun 1, 2004

Filed:

Mar 29, 2002

Appl. No.:

10/113378

Inventors:

Jiri L. Vasat - Chesterfield MO
Andrei Stefanescu - OFallon MO
Thomas A. Torack - Oakland MO
Gregory M. Wilson - Chesterfield MO

Assignee:

MEMC Electronic Materials, Inc. - St. Peters MO

International Classification:

H01L 2906

US Classification:

428 641, 428446, 117 3, 117928, 423348

Abstract:

A process for manufacturing silicon wafers that reduces the size of silicon wafer surface and/or sub-surface defects without the forming excessive haze. The process entails cleaning the front surface of the silicon wafer at a temperature of at least about 1100Â C. by exposing the front surface to a cleaning ambient comprising H , HF gas, or HCl gas to remove silicon oxide from the front surface and exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100Â C. to a vacuum or an annealing ambient consisting essentially of a mono-atomic noble gas selected from the group consisting of He, Ne, Ar, Kr, and Xe to facilitate the migration of silicon atoms to the exposed agglomerated defects without substantially etching silicon from the front surface of the heated silicon wafer.

US Patent:

6958092, Oct 25, 2005

Filed:

Mar 25, 2003

Appl. No.:

10/400594

Inventors:

Gregory M. Wilson - Chesterfield MO, US
Jon A. Rossi - Mountainview CA, US
Charles C. Yang - Gilbert AZ, US

Assignee:

MEMC Electronic Materials, Inc. - St. Peters MO

International Classification:

C30B015/02

US Classification:

117 23, 117 89, 117935, 428450, 4283105

Abstract:

A wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies, wherein the concentration of crystal lattice vacancies in the bulk layer are greater than the concentration of crystal lattice vacancies in the front surface layer. In addition, the front surface of the wafer has an epitaxial layer, having a thickness of less than about 2. 0 çm, deposited thereon. A process comprises heating a surface of a wafer starting material to remove a silicon oxide layer from the surface and depositing an epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant, and the wafer is cooled at a rate of at least about 10C. /sec.

US Patent:

20020088389, Jul 11, 2002

Filed:

Nov 15, 2001

Appl. No.:

10/001716

Inventors:

Srikanth Kommu - St. Peters MO, US
Gregory Wilson - Chesterfield MO, US

Assignee:

MEMC Electronic Materials, Inc.

International Classification:

C30B023/00
C30B025/00
C30B028/12
C30B028/14
C30B001/00
H01L021/20
H01L021/36
C23C016/00

US Classification:

117/093000, 118/728000, 117/105000

Abstract:

A method and apparatus for the high throughput epitaxial growth of a layer on the surface of a substrate by chemical vapor deposition is provided. In one embodiment, the method of the present invention comprises placing the substrate within a reactor vessel and passing a horizontal flow of reactant gas comprising a precursor chemical through the reactor vessel. The flow of the reactant gas is defined as having a Reynolds number of at least about 5000. The substrate is heated to a temperature sufficient to thermally decompose the precursor chemical and deposit an epitaxial layer on the substrate. In accordance with a preferred embodiment of the present invention, the substrate is placed within the reactor vessel at a position such that the flow of the reactant gas is characterized as a fully developed turbulent flow.

US Patent:

20020127766, Sep 12, 2002

Filed:

Dec 21, 2001

Appl. No.:

10/036917

Inventors:

Michael Ries - St. Charles MO, US
Gregory Wilson - Chesterfield MO, US
Robert Standley - Chesterfield MO, US
Larry Shive - St. Peters MO, US
Jon Rossi - Chesterfield MO, US

Assignee:

MEMC Electronic Materials, Inc.

International Classification:

H01L021/00
C30B023/00
C30B028/12
C30B025/00
C30B028/14

US Classification:

438/094000

Abstract:

A process for manufacturing a semiconductor wafer comprises first etching the wafer to reduce damage on the front and back surfaces. An epitaxial layer is grown on the etched front surface of the semiconductor wafer to improve the surface roughness of the front surface. Finally, the front surface of the wafer is final polished to further improve the surface roughness of the front surface.

US Patent:

20050032337, Feb 10, 2005

Filed:

Sep 14, 2004

Appl. No.:

10/940824

Inventors:

Gregory Wilson - Chesterfield MO, US
Michael Ries - St. Charles MO, US

International Classification:

H01L021/322

US Classification:

438476000

Abstract:

An apparatus and method are provided for forming an epitaxial layer on and denuded zone in a semiconductor wafer used in manufacturing electronic components. The denuded zone and epitaxial layer are formed in one apparatus. The apparatus includes a Bernoulli wand that is used to support the wafer in a cooling position to effect fast cooling of the wafer and formation of the denuded zone.

US Patent:

20060138601, Jun 29, 2006

Filed:

Apr 13, 2005

Appl. No.:

11/104544

Inventors:

Michael Seacrist - Ballwin MO, US
Gregory Wilson - Chesterfield MO, US
Robert Standley - Chesterfield MO, US

Assignee:

MEMC Electronic Materials, Inc. - St. Peters MO

International Classification:

H01L 23/58

US Classification:

257631000, 257E29068

Abstract:

A heteroepitaxial semiconductor wafer includes a heteroepitaxial layer forming the front surface of the wafer that includes a secondary material having a different crystal structure than that of the wafer primary material. The heteroepitaxial layer is substantially free of defects. A surface layer includes the primary material and is free of the secondary material. The surface layer borders the heteroepitaxial layer. A bulk layer includes the primary material and is free of the secondary material. The bulk layer borders the surface layer and extends through the central plane. An SOI wafer and a method of making wafers is disclosed.

US Patent:

20100130021, May 27, 2010

Filed:

Nov 23, 2009

Appl. No.:

12/623863

Inventors:

Michael J. Ries - St. Charles MO, US
Robert W. Standley - Chesterfield MO, US
Jeffrey L. Libbert - O'Fallon MO, US
Andrew M. Jones - Wildwood MO, US
Gregory M. Wilson - Chesterfield MO, US

Assignee:

MEMC ELECTRONIC MATERIALS, INC. - St. Peters MO

International Classification:

H01L 21/306

US Classification:

438748, 257E21219

Abstract:

A method is disclosed for processing the cleaved surface of a silicon-on-insulator structure. The silicon-on-insulator structures comprises a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The methods disclosed include an etching process to reduce the time and cost required to process the silicon-on-insulator structure to remove the surface damage and defects formed when a portion of the donor wafer is separated along a cleave plane from the silicon-on-insulator structure. The method includes, annealing the structure, etching the cleaved surface, and performing a non-contact smoothing process on the cleaved surface.