Huyen D Tran

US Patent:

6638810, Oct 28, 2003

Filed:

Nov 5, 2001

Appl. No.:

10/015203

Inventors:

Mouloud Bakli - Crolles, FR
Steve G. Ghanayem - Los Altos CA
Huyen T. Tran - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 218242

US Classification:

438240, 438396, 438608, 438635, 438660, 438663, 438785

Abstract:

The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and ammonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to forma metal/metal nitride liner/barrier scheme. The invention further provides a process to form a microelectronic device comprising forming a first electrode, forming a metal nitride layer over the first electrode by densifying a metal oxide layer by a nitrating gas to form a metal nitride layer, depositing a dielectric layer over the metal nitride layer, and forming a second electrode over the dielectric layer.

US Patent:

20060196778, Sep 7, 2006

Filed:

Jan 27, 2006

Appl. No.:

11/342179

Inventors:

Renhe Jia - Berkeley CA, US
Zhihong Wang - Santa Clara CA, US
Yuan Tian - San Jose CA, US
Huyen Tran - Sunnyvale CA, US
Daxin Mao - Cupertino CA, US
Stan Tsai - Fremont CA, US
Lakshmanan Karuppiah - San Jose CA, US
Liang-Yuh Chen - Foster City CA, US

International Classification:

B23H 9/00
C25D 17/00

US Classification:

205640000, 20422400M

Abstract:

Methods for polishing tungsten are provided. During ECMP, increasing the voltage to the pad is not always enough to increase the polishing rate. When polishing tungsten, simply increasing the applied voltage will, in some cases, actually decrease the removal rate. By increasing the down force pressure between the polishing pad and the substrate, the applied voltage, and the rotation speed of the substrate and the polishing pad, the tungsten removal rate will also increase.

US Patent:

63197669, Nov 20, 2001

Filed:

Feb 22, 2000

Appl. No.:

9/510582

Inventors:

Mouloud Bakli - Crolles, FR
Steve G. Ghanayem - Los Altos CA
Huyen T. Tran - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 218242

US Classification:

438240

Abstract:

The invention provides a method for forming a metal nitride film by depositing a metal oxide film on the substrate and exposing the metal oxide film to a nitrating gas to densify the metal oxide and form a metal nitride film. The metal oxide film is deposited by the decomposition of a chemical vapor deposition precursor. The nitrating step comprises exposing the metal oxide film to a thermally or plasma enhanced nitrating gas preferably comprising nitrogen, oxygen, and anunonia. The invention also provides a process for forming a liner/barrier scheme for a metallization stack by forming a metal nitride layer over the substrate by the densification of a metal oxide layer by a nitrating gas depositing a metal liner layer. Optionally, a metal liner layer may be deposited over substrate prior to the metal nitride layer to form a metal/metal nitride liner/barrier scheme. The invention firer provides a process to form a microelectronic device comprising forming a first electrode, forming a metal nitride layer over the first electrode by densifying a metal oxide layer by a nitrating gas to form a metal nitride layer, depositing a dielectric layer over the metal nitride layer, and forming a second electrode over the dielectric layer.

US Patent:

60444223, Mar 28, 2000

Filed:

May 7, 1999

Appl. No.:

9/307103

Inventors:

Huyen B. Tran - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1314
G06F 902

US Classification:

710 69

Abstract:

A laptop computer contains a built-in modem and has a phone jack for connection to a telephone line while the computer is being operated in a stand-alone mode. A docking station into which the laptop computer may be docked allows the combined unit to be operated in a desk-top mode. The docking station may have a full-sized keyboard and display so that the laptop functions as the main computer a user may employ in the office or home. A telephone connection is already in place at the docking station so that the user need not make a phone line connection to invoke the docked mode, but instead merely nests the laptop in the docking station. In one embodiment, the only components of the modem that are duplicated in the docking station are the phone jack itself and an isolation and 2-to-4 wire converter, so the plug-in connector ordinarily employed between a laptop and a docking station may be of a low-voltage, spike voltage protected form, whereby the coupling used for computer logic and control levels is compatible. The possibility of damage to computer circuits due to the proximity of high-voltage telephone line connections is thus avoided.

US Patent:

59319291, Aug 3, 1999

Filed:

Dec 31, 1996

Appl. No.:

8/775593

Inventors:

Huyen B. Tran - Houston TX
Robin T. Castell - Spring TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1314
G06F 902

US Classification:

710 69

Abstract:

A laptop computer contains a built-in modem and has a phone jack for connection to a telephone line while the computer is being operated in a stand-alone mode. A docking station into which the laptop computer may be docked allows the combined unit to be operated in a desk-top mode. The docking station may have a full-sized keyboard and display so that the laptop functions as the main computer a user may employ in the office or home. A telephone connection is already in place at the docking station so that the user need not make a phone line connection to invoke the docked mode, but instead merely nests the laptop in the docking station. In one embodiment, the only components of the modem that are duplicated in the docking station are the phone jack itself and an isolation and 2-to-4 wire converter, so the plug-in connector ordinarily employed between a laptop and a docking station may be of a low-voltage, spike voltage protected form, whereby the coupling used for computer logic and control levels is compatible. The possibility of damage to computer circuits due to the proximity of high-voltage telephone line connections is thus avoided.

US Patent:

20230073926, Mar 9, 2023

Filed:

Jan 5, 2021

Appl. No.:

17/758207

Inventors:

- Mountain View CA, US
Ramesh BALIGA - Redwood City CA, US
Sachi AHMED - Fremont CA, US
Kevin CARLIN - Saratoga CA, US
Paul HINTON - Sunnyvale CA, US
Mark SMITH - Davis CA, US
Avneesh SAINI - Sunnyvale CA, US
Huyen TRAN - San Jose CA, US
Marvin PETERSON - San Ramon CA, US

International Classification:

C07K 16/46
C12N 9/10
C12N 5/00
C12N 15/85

Abstract:

This disclosure provides a monoclonal population of highly sialylated multimeric binding molecules where the population includes IgM antibodies, IgM-like antibodies, or other IgM-derived binding molecules, where the population of binding molecules has a higher level of sialic acid content than is found in normal serum IgM. Also provided are methods of producing such monoclonal populations of highly sialylated multimeric binding molecules.

US Patent:

20180207770, Jul 26, 2018

Filed:

Jan 19, 2018

Appl. No.:

15/875867

Inventors:

- Santa Clara CA, US
Gregory E. MENK - Pleasanton CA, US
Eric DAVEY - Mountain View CA, US
You WANG - Cupertino CA, US
Huyen Karen TRAN - San Jose CA, US
Fred C. REDEKER - Fremont CA, US
Veera Raghava Reddy KAKIREDDY - Santa Clara CA, US
Ekaterina MIKHAYLICHENKO - San Jose CA, US
Jay GURUSAMY - Santa Clara CA, US

International Classification:

B24D 11/00
H01L 21/306
C09K 3/14
B24D 3/22
B24B 37/26
B24B 37/20

Abstract:

A method and apparatus for polishing a substrate that includes a polishing article comprising a polymeric sheet having a raised surface texture, which is formed on the surface of the polymeric sheet is provided. According to one or more implementations of the present disclosure, an advanced polishing article has been developed, which does not require abrasive pad conditioning. In some implementations of the present disclosure, the advanced polishing article comprises a polymeric sheet having a polishing surface with a raised surface texture or “micro-features” and/or a plurality of grooves or “macro-features” formed in the polishing surface. In some implementations, the raised surface texture is embossed, etched, machined or otherwise formed in the polishing surface prior to installing and using the advanced polishing article in a polishing system. In one implementation, the raised features have a height within one order of magnitude of the features removed from the substrate during polishing.

US Patent:

20170151647, Jun 1, 2017

Filed:

Feb 3, 2017

Appl. No.:

15/424670

Inventors:

- Santa Clara CA, US
Wen-Chiang Tu - Mountain View CA, US
Jimin Zhang - San Jose CA, US
Ingemar Carlsson - Milpitas CA, US
Boguslaw A. Swedek - Cupertino CA, US
Zhihong Wang - Santa Clara CA, US
Stephen Jew - San Jose CA, US
David H. Mai - Palo Alto CA, US
Huyen Tran - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B24B 37/013
H01L 21/306
B24B 37/04
H01L 21/66

Abstract:

A difference between a first expected required polish time for a first substrate and a second expected required polish time for a second substrate is determined using a first pre-polish thickness and a second pre-polish thickness measured at an in-line metrology station. A duration of an initial period is determined based on the difference between the first expected required polish time and the second expected required polish time. For the initial period at a beginning of a polishing operation, no pressure is applied to whichever of the first substrate and the second substrate has a lesser expected required polish time while simultaneously pressure is applied to whichever of the first substrate and the second substrate has a greater expected required polish time. After the initial period, pressure is applied to both the first substrate and the second substrate.

Address:

2686 Murworth Dr APT 1501, Houston, TX 77054

VIN:

3N1BC13E99L390287

Make:

NISSAN

Model:

VERSA

Year:

2009