James Aaron Parrish

US Patent:

40977536, Jun 27, 1978

Filed:

Apr 2, 1976

Appl. No.:

5/673178

Inventors:

Peter William Cook - Mount Kisco NY
James Thomas Parrish - Carmel NY
Stanley Everett Schuster - Granite Springs NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 520

US Classification:

307359

Abstract:

A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement.