Jeffery Scott Patterson

US Patent:

7768355, Aug 3, 2010

Filed:

Nov 8, 2007

Appl. No.:

11/937362

Inventors:

Jeffery S. Patterson - Cloverdale CA, US

Assignee:

Agilent Technologies, Inc. - Santa Clara CA

International Classification:

H03L 7/085

US Classification:

331 1A, 331177 R, 327106, 327114

Abstract:

A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases.

US Patent:

8494105, Jul 23, 2013

Filed:

Nov 22, 2010

Appl. No.:

12/951251

Inventors:

Jeffery Patterson - Santa Rosa CA, US

Assignee:

Agilent Technologies, Inc. - Santa Clara CA

International Classification:

H03D 3/24

US Classification:

375376, 375294, 375327, 375360, 375373

Abstract:

An apparatus provides a digital representation of a time difference between a periodic reference signal having a reference signal period and a periodic input signal having an input signal period. The apparatus includes a free-running finite state machine (FSM) that traverses a multiplicity of states in a predetermined order, the state having corresponding state vectors, each of which is held for a state dwell time. A timing circuit receives the reference signal, the input signal and the FSM state vectors, and determines a state transition count equal to a number of FSM state transitions that occur during a counting interval, which corresponds to the time difference between the reference and input signals. A digital low-pass filter receives the state transition counts and provides an output value including weighted sums of the state transition counts, proportional to the time difference between the reference and input signal. A period of the FSM is independent of the reference signal period.

US Patent:

20100194444, Aug 5, 2010

Filed:

Jan 30, 2009

Appl. No.:

12/363660

Inventors:

Jeffery Patterson - Cloverdale CA, US

Assignee:

AGILENT TECHNOLGIES, INC - Loveland CO

International Classification:

H03B 21/00

US Classification:

327106

Abstract:

In an embodiment, an apparatus, comprises a phase accumulator configured to provide an output comprising a truncated phase word representative of an instantaneous phase; a multiplexer configured to provide an output representative of a phase rotation, wherein the output representative of the phase rotation is randomly selected from a group of phase rotation representation outputs; an adder configured to receive the output from the phase accumulator and the output from the multiplexer, wherein the adder provides an output representative of the instantaneous phase rotated by the phase rotation; a lookup table configured to receive the output representative of the instantaneous phase and to provide an amplitude output; and a rotator configured to receive the amplitude output and substantially to cancel the phase rotation. Other embodiments do not comprise a rotator. A method is also described.

US Patent:

58218165, Oct 13, 1998

Filed:

Jun 12, 1997

Appl. No.:

8/873784

Inventors:

Jeffery S. Patterson - Santa Rosa CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H03L 718

US Classification:

331 1A

Abstract:

A variable frequency synthesis apparatus and method use a phase prediction signal to enable integer division in the feedback path of a phase-lock-loop to provide an output signal at a rational frequency multiple of an applied reference signal. A fixed integer divide ratio is maintained within each period of the reference signal. The output signal provided by a variable frequency oscillator is frequency divided and is phase compared to the reference signal. The phase comparison produces a predictable, time-varying phase difference signal based on a known frequency difference between the output signal and the reference signal. The phase prediction signal cancels the predictable phase difference signal and isolates an phase error signal used to steer, or adjust, the frequency of the oscillator to precisely equal the rational frequency multiple of the applied reference signal when the phase error signal is minimized.

US Patent:

59364300, Aug 10, 1999

Filed:

Jul 21, 1997

Appl. No.:

8/897664

Inventors:

Jeffery S. Patterson - Santa Rosa CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H03K 526
H03D 1300

US Classification:

327 12

Abstract:

A phase detection apparatus produces a phase difference signal in response to the phase difference between two applied input signals. The phase detector includes a lead/lag indicator receiving the input signals, and a logic block receiving the input signals. The logic block generates an output signal in response to the time delay between corresponding amplitude transitions, such as rising edges, of each of the input signals. The lead/lag indicator records which one of the two input signals leads in phase and generates an enable signal that steers the output signal from the logic block to one or the other of the phase detector's two output terminals. A phase detection method generates an output signal corresponding to the phase difference between a pair of input signals by recording which one of the input signals leads in phase relative to the other of the input signals, generating a pulse having a pulse width equal to the time delay between corresponding amplitude transitions of the input signals, delaying the pulse and then steering the pulse to one of the output terminals according to which one of the input signals is recorded as leading in phase.

US Patent:

58835369, Mar 16, 1999

Filed:

Jun 12, 1997

Appl. No.:

8/873494

Inventors:

Jeffery S. Patterson - Santa Rosa CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G01R 2508

US Classification:

327184

Abstract:

A phase detector provides a digital output having a linear relationship to the phase difference between a reference signal and an applied input signal. The phase detector counts the number of cycles of the reference signal within a time interval determined by the difference in arrival times of corresponding amplitude transitions of the reference signal and the input signal. A digital output representing the number of counted cycles is produced. A dither generator adds random time variation to the time interval over which the reference signal cycles are counted to introduce a corresponding random variation in the digital output.