Jeffrey W Chee

US Patent:

20200350202, Nov 5, 2020

Filed:

May 1, 2019

Appl. No.:

16/400481

Inventors:

- Grand Cayman, KY
Haiting Wang - Clifton Park NY, US
Hong Yu - Clifton Park NY, US
Jeffrey Chee - Ballston Lake NY, US
Guoliang Zhu - Rexford NY, US

International Classification:

H01L 21/768
H01L 23/528
H01L 23/522
H01L 21/033

Abstract:

Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.

US Patent:

20200266286, Aug 20, 2020

Filed:

Feb 20, 2019

Appl. No.:

16/280343

Inventors:

- Grand Cayman, KY
Sipeng Gu - Clifton Park NY, US
Jeffrey Chee - Ballston Lake NY, US
Keith H. Tabakman - Gansevoort NY, US

International Classification:

H01L 29/66
H01L 29/423
H01L 29/06
H01L 21/768
H01L 21/8234
H01L 21/311

Abstract:

A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.

US Patent:

20190221515, Jul 18, 2019

Filed:

Jan 16, 2018

Appl. No.:

15/872589

Inventors:

- Grand Cayman, KY
Jianwei Peng - Latham NY, US
Xusheng Wu - Ballston Lake NY, US
Yi Qi - Niskayuna NY, US
Jeffrey Chee - Ballston Lake NY, US

International Classification:

H01L 23/522
H01L 49/02
H01L 21/768

Abstract:

Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

US Patent:

20180240703, Aug 23, 2018

Filed:

Feb 22, 2017

Appl. No.:

15/438828

Inventors:

- GRAND CAYMAN, KY
XUSHENG WU - BALLSTON LAKE NY, US
XINYUAN DOU - CLIFTON PARK NY, US
XIAOBO CHEN - REXFORD NY, US
GUOLIANG ZHU - REXFORD NY, US
WENHE LIN - SARATOGA SPRINGS NY, US
JEFFREY CHEE - BALLSTON LAKE NY, US

Assignee:

GLOBALFOUNDRIES INC. - GRAND CAYMAN

International Classification:

H01L 21/768
H01L 23/535
H01L 23/532

Abstract:

Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

US Patent:

20180233566, Aug 16, 2018

Filed:

Apr 18, 2018

Appl. No.:

15/956090

Inventors:

- GRAND CAYMAN, KY
XUSHENG WU - BALLSTON LAKE NY, US
WENHE LIN - SARATOGA SPRINGS NY, US
JEFFREY CHEE - BALLSTON LAKE NY, US

Assignee:

GLOBALFOUNDRIES INC. - GRAND CAYMAN

International Classification:

H01L 29/417
H01L 29/78
H01L 29/66
H01L 21/265
H01L 29/08
H01L 21/321

Abstract:

Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.

US Patent:

20180204920, Jul 19, 2018

Filed:

Jan 19, 2017

Appl. No.:

15/410159

Inventors:

- Grand Cayman, KY
XUSHENG WU - BALLSTON LAKE NY, US
WENHE LIN - SARATOGA SPRINGS NY, US
JEFFREY CHEE - BALLSTON LAKE NY, US

Assignee:

GLOBALFOUNDRIES INC. - GRAND CAYMAN

International Classification:

H01L 29/417
H01L 29/66
H01L 21/321
H01L 29/78
H01L 29/08
H01L 21/265

Abstract:

Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.