Jeffrey L Shields

US Patent:

7466591, Dec 16, 2008

Filed:

Jun 1, 2006

Appl. No.:

11/421734

Inventors:

Jeffrey A. Shields - Chandler AZ, US
Kent Hewitt - Chandler AZ, US
Donald Gerber - Scottsdale AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 11/34

US Classification:

36518518, 257315

Abstract:

A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

US Patent:

7817474, Oct 19, 2010

Filed:

Dec 10, 2008

Appl. No.:

12/331542

Inventors:

Jeffrey A. Shields - Chandler AZ, US
Kent D. Hewitt - Chandler AZ, US
Donald S. Gerber - Scottsdale AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 16/00

US Classification:

36518518, 36518527, 36518529

Abstract:

A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

US Patent:

8094503, Jan 10, 2012

Filed:

Aug 11, 2010

Appl. No.:

12/854504

Inventors:

Jeffrey A. Shields - Chandler AZ, US
Kent D. Hewitt - Chandler AZ, US
Donald S. Gerber - Scottsdale AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 16/04

US Classification:

36518518, 36518502, 36518527, 36518528

Abstract:

A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

US Patent:

20020006059, Jan 17, 2002

Filed:

Apr 23, 2001

Appl. No.:

09/839236

Inventors:

Donald Gerber - Gilbert AZ, US
Kent Hewitt - Chandler AZ, US
Jeffrey Shields - Chandler AZ, US

International Classification:

G11C011/34

US Classification:

365/185020

Abstract:

A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.

US Patent:

20070140008, Jun 21, 2007

Filed:

Dec 21, 2005

Appl. No.:

11/314504

Inventors:

Jeffrey Shields - Chandler AZ, US
Kent Hewitt - Chandler AZ, US
Donald Gerber - Scottsdale AZ, US
Randy Yach - Phoenix AZ, US

International Classification:

G11C 16/04
G11C 11/34

US Classification:

365185110, 365185180

Abstract:

An array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

US Patent:

62365959, May 22, 2001

Filed:

Jul 17, 2000

Appl. No.:

9/617280

Inventors:

Donald S. Gerber - Gilbert AZ
Kent Hewitt - Chandler AZ
Jeffrey A. Shields - Chandler AZ
David M. Davies - Phoenix AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 1604

US Classification:

36518518

Abstract:

A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.

US Patent:

62227610, Apr 24, 2001

Filed:

Jul 17, 2000

Appl. No.:

9/617281

Inventors:

Donald S. Gerber - Gilbert AZ
Kent Hewitt - Chandler AZ
Jeffrey A. Shields - Chandler AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 1604

US Classification:

36518502

Abstract:

A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.

US Patent:

20140269102, Sep 18, 2014

Filed:

Mar 13, 2014

Appl. No.:

14/209275

Inventors:

- Chandler AZ, US
Jack Wong - Phoenix AZ, US
Bomy Chen - Newark CA, US
Sonu Daryanani - Tempe AZ, US
Jeffrey A. Shields - Chandler AZ, US
Daniel Alvarez - Gilbert AZ, US
Mel Hymas - Camas WA, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G11C 16/10

US Classification:

36518529, 36518518

Abstract:

An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.