Jennifer Y Tseng

US Patent:

6645550, Nov 11, 2003

Filed:

Jun 22, 2000

Appl. No.:

09/599125

Inventors:

Robin Cheung - Cupertino CA
Yezdi Dordi - Palo Alto CA
Jennifer Tseng - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B05D 102

US Classification:

427123, 427261, 427287, 427328, 427343, 427404, 427405, 427421

Abstract:

A method of treating a substrate. The method comprises forming a metal-containing layer on at least a selected portion of the substrate during a substrate cleaning process.

US Patent:

20020033533, Mar 21, 2002

Filed:

Mar 28, 1997

Appl. No.:

08/825360

Inventors:

MARVIN LIAO - WOODBRIDGE, SG
CHYI CHERN - SARATOGA CA, US
JENNIFER TSENG - SARATOGA CA, US
MICHAEL DANEK - SUNNYVALE CA, US
RODERICK C MOSELY - PLEASANTON CA, US
KARL LITTAU - PALO ALTO CA, US

International Classification:

H01L021/4763
H01L023/48
H01L023/52
H01L029/40

US Classification:

257/751000

Abstract:

A structure is formed in an integrated circuit to provide for the coupling of elements in the integrated circuit. The structure extends from a conductive surface through a channel extending above the conductive surface. The structure includes a layer of a refractory metal, a layer of a metal nitride, and a layer of a metal. The layer of the refractory metal is deposited on the conductive surface and inner walls of the channel. The layer of the metal nitride is formed on the layer of the refractory metal. The layer of the metal nitride has a thickness extending from the layer of the refractory metal of less than 130 . The layer of the metal is deposited on the layer of the metal nitride.

US Patent:

20130292806, Nov 7, 2013

Filed:

May 30, 2013

Appl. No.:

13/905932

Inventors:

Paul F. Ma - Santa Clara CA, US
Jennifer Meng Tseng - Saratoga CA, US
Mei Chang - Saratoga CA, US
Annamalai Lakshmanan - Fremont CA, US
Jing Tang - Cupertino CA, US

International Classification:

H01L 29/06
H01L 21/02

US Classification:

257632, 438758

Abstract:

Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer.

US Patent:

62913433, Sep 18, 2001

Filed:

Jan 20, 1998

Appl. No.:

9/008796

Inventors:

Jennifer Tseng - Saratoga CA
Mei Chang - Saratoga CA
Ling Chen - Sunnyvale CA
David C. Smith - Santa Clara CA
Karl A. Littau - Palo Alto CA
Chyi Chern - Saratoga CA
Marvin Liao - Woodbridge, SG

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2124
B05D 300
H05H 100

US Classification:

438653

Abstract:

A layer of material is formed on a substrate in a partially formed integrated circuit on a wafer. The substrate undergoes a plasma annealing, during which the substrate is bombarded with ions. The plasma annealing may be performed by exposing the substrate to plasma that is generated from a nitrogen containing gas which is infused with energy. After the substrate is plasma annealed, a layer of a refractory metal nitride is deposited on the substrate. The layer of refractory metal nitride is then bombarded with a first set of ions. The bombardment of the refractory metal by the first set of ions may be achieved by performing a plasma annealing. The refractory metal nitride may be further bombarded by a second set of ions.