Jesse P Wilson

Address:

7608 Burr Fry Dr, McKinney, TX 75071

VIN:

1FTPW12V07KB72796

Make:

FORD

Model:

F-150

Year:

2007

US Patent:

53697529, Nov 29, 1994

Filed:

Jun 1, 1992

Appl. No.:

7/891241

Inventors:

Grady L. Giles - Austin TX
William D. Atwell - Austin TX
Jesse R. Wilson - Austin TX
Richard B. Reis - Garland TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1202

US Classification:

395425

Abstract:

A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.

US Patent:

48020869, Jan 31, 1989

Filed:

Jan 9, 1987

Appl. No.:

7/002335

Inventors:

James G. Gay - Pflugerville TX
Jesse R. Wilson - Austin TX
William C. Moyer - Dripping Springs TX
Terry V. Hulett - San Antonio TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A cache location selector selects locations in a cache for loading new information using either a valid chain, if not all locations already contain valid information, or a history loop otherwise. The valid chain selects the "highest" location in the cache which does not already contain valid information. The history loop selects locations in accordance with a modified form of the First-In-Not-Used-First-Out (FINUFO) replacement scheme. Both the valid chain and the history loop are fully and efficiently implemented in hardware. During normal cache operation, both the valid chain and the history loop continuously seek an appropriate location to be used for the next load. As a result, that location is preselected well before the load is actually required.

US Patent:

46807608, Jul 14, 1987

Filed:

Aug 5, 1985

Appl. No.:

6/762656

Inventors:

Grady L. Giles - Austin TX
Jesse R. Wilson - Austin TX
Terry V. Hulett - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 100

US Classification:

371 21

Abstract:

Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.

US Patent:

44881517, Dec 11, 1984

Filed:

Dec 10, 1981

Appl. No.:

6/329424

Inventors:

Brent C. Bolton - Austin TX
Gary L. Logsdon - Round Rock TX
Carl F. Hagenmaier - Pittstown NJ
Jesse R. Wilson - Austin TX

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

H04Q 900
H04J 302

US Classification:

3408255

Abstract:

Disclosed is an arbiter switch for use in forming an asynchronous network of concurrent processors where the arbiter switch receives a message from one of two input ports and transmits it to its output port. A path through the network which has been established can be cleared should it become apparent that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.

US Patent:

55725350, Nov 5, 1996

Filed:

Jul 5, 1994

Appl. No.:

8/270601

Inventors:

Carl Pixley - Austin TX
Hyunwoo Cho - Austin TX
Bernard F. Plessier - Austin TX
Jesse R. Wilson - Austin TX
Ralph McGarity - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

G06F 1134
G11C 2900

US Classification:

371 221

Abstract:

A method (FIGS. 12-16) and a data processing system (FIG. 4) are used to verify the correct operation of one or more tri-state multiplexers (FIG. 3) located in a circuit model (37). The tri-state multiplexer checker (38) accesses the circuit model (37) and identifies the tri-state multiplexer(s). Once identified these tri-state multiplexers are checked to ensure that: (1) no two or more select/control lines to a tri-state MUX are enabled at a critical point in time wherein tri-state MUX output line contention can occur (i. e. both a logic zero and a logic one are being driven to the MUX output); and (2) that at least one select/control line is enabled during all critical periods of time so that a high impedance (high-Z) state is not propagated incorrectly through the MUX. This checking/verification is performed in a cut-set manner which is iterative and very time efficient when compared to prior methods.

US Patent:

50158759, May 14, 1991

Filed:

Dec 1, 1989

Appl. No.:

7/444208

Inventors:

Grady L. Giles - Austin TX
Jesse R. Wilson - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 3284
H03K 19007

US Classification:

3072722

Abstract:

A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic. Thus, the logic under test is not affected by the loading of the scan test vector, since the parallel system output Q of the TFSFF does not toggle during the shifting sequence.

US Patent:

44751885, Oct 2, 1984

Filed:

Sep 2, 1982

Appl. No.:

6/414069

Inventors:

Jesse R. Wilson - Austin TX
Gary L. Logsdon - Round Rock TX

Assignee:

Burroughs Corp. - Detroit MI

International Classification:

H04J 600

US Classification:

370 60

Abstract:

A four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors, each port of the module including an input selector switch and an output selector switch such that each selector switch has a plurality of output channels one for each of the output arbiter switches (except the arbiter switch associated with its own port). Each selector switch is adapted to select a particular output channel (arbiter switch) according to the initial bits received in the asynchronous speed independent message. In this manner, the module of the present invention can accommodate up to five simultaneous asynchronous message transmissions without nodal blocking although the average number of simultaneous messages that can be accommodated will be less. The respective arbiter and selector switches are provided with circuitry to respond to a clear signal that resets the corresponding arbiter and selector switches forming a particular transmission path should nodal blocking occur.

US Patent:

44981333, Feb 5, 1985

Filed:

Dec 10, 1981

Appl. No.:

6/329423

Inventors:

Brent C. Bolton - Austin TX
Gary L. Logsdon - Round Rock TX
Carl F. Hagenmaier - Pittstown NJ
Jesse R. Wilson - Austin TX

Assignee:

Burroughs Corp. - Detroit MI

International Classification:

G06F 900

US Classification:

364200

Abstract:

Disclosed is a selector switch for use in forming an asynchronous network of concurrent processors where the selector switch receives a message from one input port and transmits it to one of two output ports. A path through the network which has been established can be cleared should it become apparent that that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.