Jian Huan Tan

US Patent:

6445245, Sep 3, 2002

Filed:

Oct 6, 2000

Appl. No.:

09/684539

Inventors:

David P. Schultz - San Jose CA
Suresh M. Menon - Sunnyvale CA
Eunice Y. D. Hao - Saratoga CA
Jason R. Bergendahl - Campbell CA
Jian Tan - Milpitas CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G05F 110

US Classification:

327541, 327543

Abstract:

A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

US Patent:

6489837, Dec 3, 2002

Filed:

Nov 30, 2001

Appl. No.:

10/007167

Inventors:

David P. Schultz - San Jose CA
Suresh M. Menon - Sunnyvale CA
Eunice Y. D. Hao - Saratoga CA
Jason R. Bergendahl - Campbell CA
Jian Tan - Milpitas CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G05F 110

US Classification:

327541, 327566, 36523003

Abstract:

A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

US Patent:

6810458, Oct 26, 2004

Filed:

Mar 1, 2002

Appl. No.:

10/090257

Inventors:

Hassan K. Bazargan - San Jose CA
Jian Tan - Milpitas CA
Atul V. Ghia - San Jose CA
Suresh M. Menon - Sunnyvale CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

710302, 710301, 326 87

Abstract:

A hot swap protection circuit ( ) for an integrated circuit being plugged into a powered-up system includes a first circuit ( ) for detecting a hot swap condition, a second circuit ( ) coupled to the first circuit for preventing a pn junction diode ( ) in a pull-up transistor ( ) from going into a forward bias condition, and a third circuit ( ) coupled to the first and second circuits for preventing the pull-up transistor from turning on during the hot swap condition.

US Patent:

6985096, Jan 10, 2006

Filed:

Aug 17, 2004

Appl. No.:

10/919900

Inventors:

Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Jian Tan - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 9/00

US Classification:

341100, 341101

Abstract:

Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.

US Patent:

7091890, Aug 15, 2006

Filed:

Aug 17, 2004

Appl. No.:

10/919901

Inventors:

Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Hassan Bazargan - San Jose CA, US
Ketan Sodha - Fremont CA, US
Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US
Suresh Menon - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 9/00

US Classification:

341100, 341 59

Abstract:

A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

US Patent:

7468615, Dec 23, 2008

Filed:

Mar 28, 2007

Appl. No.:

11/729201

Inventors:

Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/094
H03K 19/0175
H03L 5/00

US Classification:

326 68, 327333

Abstract:

A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency. The level shifter maintains rise time, fall time, and duty cycle over a wide range of input and output voltage levels.

US Patent:

7589557, Sep 15, 2009

Filed:

Apr 18, 2006

Appl. No.:

11/405901

Inventors:

Jason R. Bergendahl - Sunnyvale CA, US
Qi Zhang - Milpitas CA, US
Jian Tan - Fremont CA, US
Matthew H. Klein - Redwood City CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 41, 326 37

Abstract:

An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e. g. , by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

US Patent:

7839173, Nov 23, 2010

Filed:

Aug 11, 2009

Appl. No.:

12/539522

Inventors:

Wenfeng Zhang - San Jose CA, US
Qi Zhang - Chandler AZ, US
Jian Tan - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 81, 326 87

Abstract:

A system for signal level shifting in an IC can include a first inverter having a first pull-up device and a pull-down device, wherein the first inverter is operable to receive an input signal having a voltage potential at a logic high that does not disable the first pull-up device. The system can include a second inverter coupled in series to an output of the first inverter, and a control module coupled to the output of the first inverter and an output of the second inverter. Prior to the input signal transitioning to the logic high, the control module is operable to decouple the input signal from the first pull-up device, disable the first pull-up device, and close a feedback loop that latches an output state of the second inverter.