Jian Ming Tan

US Patent:

6985096, Jan 10, 2006

Filed:

Aug 17, 2004

Appl. No.:

10/919900

Inventors:

Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Jian Tan - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 9/00

US Classification:

341100, 341101

Abstract:

Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.

US Patent:

7091890, Aug 15, 2006

Filed:

Aug 17, 2004

Appl. No.:

10/919901

Inventors:

Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Hassan Bazargan - San Jose CA, US
Ketan Sodha - Fremont CA, US
Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US
Suresh Menon - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 9/00

US Classification:

341100, 341 59

Abstract:

A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

US Patent:

7468615, Dec 23, 2008

Filed:

Mar 28, 2007

Appl. No.:

11/729201

Inventors:

Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/094
H03K 19/0175
H03L 5/00

US Classification:

326 68, 327333

Abstract:

A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency. The level shifter maintains rise time, fall time, and duty cycle over a wide range of input and output voltage levels.

US Patent:

7589557, Sep 15, 2009

Filed:

Apr 18, 2006

Appl. No.:

11/405901

Inventors:

Jason R. Bergendahl - Sunnyvale CA, US
Qi Zhang - Milpitas CA, US
Jian Tan - Fremont CA, US
Matthew H. Klein - Redwood City CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 41, 326 37

Abstract:

An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e. g. , by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

US Patent:

8018250, Sep 13, 2011

Filed:

Oct 19, 2010

Appl. No.:

12/907850

Inventors:

Matthew H. Klein - Redwood City CA, US
Jian Tan - Fremont CA, US
Ketan Sodha - Fremont CA, US
Madan M. Patra - Santa Clara CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/00
H03K 19/02

US Classification:

326 56, 326 30, 710302, 710304

Abstract:

An embodiment of a method for operation of an input/output block is disclosed. For this embodiment of the method, a first attribute is set for a first disable signal for an input driver. A first tri-state condition is removed from an output driver. In response to the removing of the first tri-state condition, the input driver is placed in a second tri-state condition.

US Patent:

8030967, Oct 4, 2011

Filed:

Jan 30, 2009

Appl. No.:

12/363653

Inventors:

Jian Tan - Fremont CA, US
Matthew H. Klein - Redwood City CA, US
Atul V. Ghia - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/094
H03K 3/00
H03B 1/00

US Classification:

326 83, 327108

Abstract:

A circuit has a programmable mode control section, and a receiver section with first and second input terminals and an output terminal. The method and apparatus involve setting the mode control section to one of first and second states in response to user input, and operating the receiver section in first and second operational mode when the mode control section respectively has the first and second states, wherein in the first operational mode the receiver section provides higher performance and consumes more power than in the second operational mode.