Jian Hui Zhao

US Patent:

53230302, Jun 21, 1994

Filed:

Sep 24, 1993

Appl. No.:

8/126837

Inventors:

Thomas E. Koscica - Clark NJ
Jian H. Zhao - North Brunswick NJ

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

H01L 29161
H01L 29205

US Classification:

257195

Abstract:

The present Field Effect Real Space Transistor, or FERST, is a four terminal device with S, G, C, and D representing the source, gate, collector, and drain, respectively. The S, G, and D terminals can be likened to those of the MODFET. The collector name is borrowed from other real space transfer devices. Surrounding the entire device is an oxygen implant isolation. The source and drain ohmic contacts penetrate to the 150. ANG. GaAs channel while the collector ohmic contact does not penetrate due to its position upon an elevated submesa. AlGaAs layers are used as etch stops during processing of the device and a Schottky barrier gate is placed on an undoped layer. Channel carriers are provided by modulation doping the lower barrier of the channel. An Al. sub. 35 Ga. sub. 65 As layer on the upper channel side is used as a real space transfer barrier. In operation and under appropriate bias conditions, real space transfer occurs across this upper barrier and into the collector.

US Patent:

52910415, Mar 1, 1994

Filed:

Mar 1, 1993

Appl. No.:

8/024699

Inventors:

Terence Burke - Ocean NJ
Maurice Weiner - Ocean NJ
Jian H. Zhao - North Brunswick NJ

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

H01L 2714
H01L 3100
H01L 2974

US Classification:

257184

Abstract:

The present invention comprises a semi-insulating layer of GaAs with p+ and layers of aluminum gallium arsenide AlGaAs grown on one side of the semi-insulating GaAs and with p and n+ layers of AlGaAs grown on the other side of the semi-insulating GaAs. Ohmic contacts are grown on both sides of the thyristor as well as low temperature GaAs to provide for surface passivity.

US Patent:

55699430, Oct 29, 1996

Filed:

Sep 1, 1995

Appl. No.:

8/522894

Inventors:

Thomas E. Koscica - Clark NJ
Jian H. Zhao - North Brunswick NJ

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

H01L 310328
H01L 310336
H01L 2980

US Classification:

257192

Abstract:

A heterostructure semiconductor device having source and drain electrodes sistively coupled to opposite ends of a channel, a barrier layer on one side of the channel, a delta doped layer in the channel or within a given distance of it, a gate electrode on the barrier so as to form a Schottky diode and at least one collector electrode mounted on said barrier layer. The collector electrode or electrodes can be resistively coupled to the barrier layer, but preferably the coupling is such as to form a Schottky diode. Changes to the gate bias affect the source current through the field effect mechanism. The collector current depends on the transfer of heated, energized carriers out of the channel over the front heterobarrier. At low gate bias, electrons entering the source travel to the drain while none travel to the collector. Energized carriers are localized to the depletion region due its high electric field drop.