Jian Hua Zhao

US Patent:

6423986, Jul 23, 2002

Filed:

Dec 8, 2000

Appl. No.:

09/719327

Inventors:

Jian J. Zhao - North Brunswick NJ

Assignee:

Rutgers, The State University - New Brunswick NJ

International Classification:

H01L 2987

US Classification:

257138, 257139, 257133, 257110, 257147, 257134

Abstract:

Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. The top semiconductor layer forms a control layer ( ). A semiconductor layer junction, remote from both device surfaces, forms a blocking p-n junction ( ) capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region ( ) extending from the top surface into the control layer ( ). A conductive tub region ( ), spaced apart from the top conductive region ( ), extends from the top surface at least through the control layer ( ). A field effect region ( ) is disposed in the control layer ( ) between the top conductive region ( ) and tub region ( ). A gate contact ( ) is formed over the field effect region ( ) causing the creation and interruption of a conductive channel ( ) between the top conductive region ( ) and conductive tub region ( ) so as to turn the device on and off.

US Patent:

6841812, Jan 11, 2005

Filed:

Nov 7, 2002

Appl. No.:

10/289907

Inventors:

Jian Hui Zhao - North Brunswick NJ, US

Assignee:

United Silicon Carbide, Inc. - New Brunswick NJ

International Classification:

H01L 2980
H01L 2976
H01L 2994

US Classification:

257256, 257329, 257341

Abstract:

The present invention is a power semiconductor switch having a monolithically integrated low-voltage lateral junction field effect transistor (LJFET) controlling a high-voltage vertical junction field effect transistor (VJFET). The low-voltage LJFET conducting channel is double-gated by p+n junctions at opposite sides of the lateral channel. A buried p-type epitaxial layer forms one of the two p+n junction gates. A p+ region created by ion implantation serves as the p+ region for the second p+n junction gate. Both gates are electrically connected by a p+ tub implantation. The vertical channel of the vertical JFET is formed by converting part of the buried p-type epitaxial layer into n+ channel via n-type ion implantation.

US Patent:

7479672, Jan 20, 2009

Filed:

Apr 9, 2007

Appl. No.:

11/784613

Inventors:

Jian H. Zhao - North Brunswick NJ, US

Assignee:

Rutgers, The State University - New Brunswick NJ

International Classification:

H01L 29/80

US Classification:

257256, 257134, 257135, 257272, 257192, 257195, 257274, 257E27148

Abstract:

A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer. A gate contact is formed on the bottom of the U-shaped trenches for the purpose of creating and interrupting the vertical channels so as to turn on and turn off the transistor.

US Patent:

8129886, Mar 6, 2012

Filed:

Feb 29, 2008

Appl. No.:

12/040287

Inventors:

Jian Zhong Zhao - Laveen AZ, US
Alan Chi-Chung Tai - Phoenix AZ, US
Dwayne Quatier - Chandler AZ, US
Kevin Mahoney - Phoenix AZ, US

Assignee:

General Electric Company - Schenectady NY

International Classification:

H01L 41/08

US Classification:

310334

Abstract:

An acoustical stack for use within an ultrasound transducer that has a center frequency has a poled piezoelectric material layer and at least one impedance matching layer. The poled piezoelectric material layer has top and bottom sides and is formed of poled piezoelectric material that has a first acoustic impedance. The poled piezoelectric material layer has a first thickness and the acoustical stack has an output electrical impedance based on the first thickness. The impedance matching layers are configured to be attached to the top and bottom sides of the poled piezoelectric material layer and have second or third thicknesses. The impedance matching layers are formed of one or more materials that have an acoustic impedance substantially similar to the first acoustic impedance. The poled piezoelectric layer and impedance matching layers form an acoustic resonance thickness. The center frequency of the transducer is based on the acoustic resonance thickness.

US Patent:

20050067630, Mar 31, 2005

Filed:

Sep 25, 2003

Appl. No.:

10/671233

Inventors:

Jian Zhao - North Brunswick NJ, US

International Classification:

H01L029/74
H01L031/111

US Classification:

257134000, 257135000, 257136000

Abstract:

A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer. A gate contact is formed on the bottom of the U-shaped trenches for the purpose of creating and interrupting the vertical channels so as to turn on and turn off the transistor.

US Patent:

20100148224, Jun 17, 2010

Filed:

Jan 19, 2009

Appl. No.:

12/355978

Inventors:

Jian H. Zhao - North Brunswick NJ, US

Assignee:

Rutgers, The State University of New Jersey - New Brunswick NJ

International Classification:

H01L 29/80

US Classification:

257263, 257E2931

Abstract:

A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer. A gate contact is formed on the bottom of the U-shaped trenches for the purpose of creating and interrupting the vertical channels so as to turn on and turn off the transistor.

US Patent:

53230302, Jun 21, 1994

Filed:

Sep 24, 1993

Appl. No.:

8/126837

Inventors:

Thomas E. Koscica - Clark NJ
Jian H. Zhao - North Brunswick NJ

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

H01L 29161
H01L 29205

US Classification:

257195

Abstract:

The present Field Effect Real Space Transistor, or FERST, is a four terminal device with S, G, C, and D representing the source, gate, collector, and drain, respectively. The S, G, and D terminals can be likened to those of the MODFET. The collector name is borrowed from other real space transfer devices. Surrounding the entire device is an oxygen implant isolation. The source and drain ohmic contacts penetrate to the 150. ANG. GaAs channel while the collector ohmic contact does not penetrate due to its position upon an elevated submesa. AlGaAs layers are used as etch stops during processing of the device and a Schottky barrier gate is placed on an undoped layer. Channel carriers are provided by modulation doping the lower barrier of the channel. An Al. sub. 35 Ga. sub. 65 As layer on the upper channel side is used as a real space transfer barrier. In operation and under appropriate bias conditions, real space transfer occurs across this upper barrier and into the collector.

US Patent:

52910415, Mar 1, 1994

Filed:

Mar 1, 1993

Appl. No.:

8/024699

Inventors:

Terence Burke - Ocean NJ
Maurice Weiner - Ocean NJ
Jian H. Zhao - North Brunswick NJ

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

H01L 2714
H01L 3100
H01L 2974

US Classification:

257184

Abstract:

The present invention comprises a semi-insulating layer of GaAs with p+ and layers of aluminum gallium arsenide AlGaAs grown on one side of the semi-insulating GaAs and with p and n+ layers of AlGaAs grown on the other side of the semi-insulating GaAs. Ohmic contacts are grown on both sides of the thyristor as well as low temperature GaAs to provide for surface passivity.