Jian Xin Zhao

US Patent:

6423986, Jul 23, 2002

Filed:

Dec 8, 2000

Appl. No.:

09/719327

Inventors:

Jian J. Zhao - North Brunswick NJ

Assignee:

Rutgers, The State University - New Brunswick NJ

International Classification:

H01L 2987

US Classification:

257138, 257139, 257133, 257110, 257147, 257134

Abstract:

Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. The top semiconductor layer forms a control layer ( ). A semiconductor layer junction, remote from both device surfaces, forms a blocking p-n junction ( ) capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region ( ) extending from the top surface into the control layer ( ). A conductive tub region ( ), spaced apart from the top conductive region ( ), extends from the top surface at least through the control layer ( ). A field effect region ( ) is disposed in the control layer ( ) between the top conductive region ( ) and tub region ( ). A gate contact ( ) is formed over the field effect region ( ) causing the creation and interruption of a conductive channel ( ) between the top conductive region ( ) and conductive tub region ( ) so as to turn the device on and off.

US Patent:

6841812, Jan 11, 2005

Filed:

Nov 7, 2002

Appl. No.:

10/289907

Inventors:

Jian Hui Zhao - North Brunswick NJ, US

Assignee:

United Silicon Carbide, Inc. - New Brunswick NJ

International Classification:

H01L 2980
H01L 2976
H01L 2994

US Classification:

257256, 257329, 257341

Abstract:

The present invention is a power semiconductor switch having a monolithically integrated low-voltage lateral junction field effect transistor (LJFET) controlling a high-voltage vertical junction field effect transistor (VJFET). The low-voltage LJFET conducting channel is double-gated by p+n junctions at opposite sides of the lateral channel. A buried p-type epitaxial layer forms one of the two p+n junction gates. A p+ region created by ion implantation serves as the p+ region for the second p+n junction gate. Both gates are electrically connected by a p+ tub implantation. The vertical channel of the vertical JFET is formed by converting part of the buried p-type epitaxial layer into n+ channel via n-type ion implantation.

US Patent:

7479672, Jan 20, 2009

Filed:

Apr 9, 2007

Appl. No.:

11/784613

Inventors:

Jian H. Zhao - North Brunswick NJ, US

Assignee:

Rutgers, The State University - New Brunswick NJ

International Classification:

H01L 29/80

US Classification:

257256, 257134, 257135, 257272, 257192, 257195, 257274, 257E27148

Abstract:

A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer. A gate contact is formed on the bottom of the U-shaped trenches for the purpose of creating and interrupting the vertical channels so as to turn on and turn off the transistor.

US Patent:

20050067630, Mar 31, 2005

Filed:

Sep 25, 2003

Appl. No.:

10/671233

Inventors:

Jian Zhao - North Brunswick NJ, US

International Classification:

H01L029/74
H01L031/111

US Classification:

257134000, 257135000, 257136000

Abstract:

A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer. A gate contact is formed on the bottom of the U-shaped trenches for the purpose of creating and interrupting the vertical channels so as to turn on and turn off the transistor.

US Patent:

20100148224, Jun 17, 2010

Filed:

Jan 19, 2009

Appl. No.:

12/355978

Inventors:

Jian H. Zhao - North Brunswick NJ, US

Assignee:

Rutgers, The State University of New Jersey - New Brunswick NJ

International Classification:

H01L 29/80

US Classification:

257263, 257E2931

Abstract:

A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer. A gate contact is formed on the bottom of the U-shaped trenches for the purpose of creating and interrupting the vertical channels so as to turn on and turn off the transistor.

US Patent:

20120072729, Mar 22, 2012

Filed:

Apr 5, 2011

Appl. No.:

13/080593

Inventors:

Joseph M. Winograd - San Diego CA, US
Rade Petrovic - San Diego CA, US
Jian Zhao - Montrose CA, US

International Classification:

G06F 21/24

US Classification:

713176

Abstract:

Methods, devices, and computer program products facilitate the application of a content use policy based on watermarks that are embedded in a content. Watermark extraction and content screening operations, which can include the application of content usage enforcement actions, may be organized such that some or all of the operations can be conducted at different times by different devices. The watermark extraction results can be stored in a secure location and accessed by other devices at different times. These operations can be conducted by one or more trusted devices that reside in a home network. The home network can also include a gateway device that can coordinate the operations of the various network devices and/or delegate the various watermark extraction and content screening operations.

US Patent:

20120072730, Mar 22, 2012

Filed:

Apr 5, 2011

Appl. No.:

13/080598

Inventors:

Joseph M. Winograd - San Diego CA, US
Rade Petrovic - San Diego CA, US
Jian Zhao - Montrose CA, US

International Classification:

H04L 9/32

US Classification:

713176

Abstract:

Methods, devices, and computer program products facilitate the application of a content use policy based on watermarks that are embedded in a content. Watermark extraction and content screening operations, which can include the application of content usage enforcement actions, may be organized such that some or all of the operations can be conducted at different times by different devices. These operations can be conducted by one or more trusted devices that reside in a networked environment. Real-time access to a content can also be facilitated by utilizing existing watermark extraction records. To facilitate real-time access to the content, the extraction records may contain segmented authentication information that correspond to particular segments of the content that is being accessed. Additionally, or alternatively, new watermark extraction operations can be conducted in real-time to produce new watermark extraction records.

US Patent:

20120072731, Mar 22, 2012

Filed:

Apr 5, 2011

Appl. No.:

13/080605

Inventors:

Joseph M. Winograd - San Diego CA, US
Rade Petrovic - San Diego CA, US
Jian Zhao - Montrose CA, US

International Classification:

G06F 21/24

US Classification:

713176

Abstract:

Methods, devices, and computer program products facilitate the application of a content use policy based on watermarks that are embedded in a content. Watermark extraction and content screening operations, which can include the application of content usage enforcement actions, may be organized such that some or all of the operations can be conducted at different times by different devices. These operations can be conducted by one or more trusted devices that reside in a networked environment. The authenticity of various devices can be verified through the exchange of certificates that can further enable such devices to ascertain capabilities of one another. Based on the ascertained capabilities, an operational configuration for conducting watermark extraction and content screening can be determined.