Jimmy Cheng

US Patent:

55600018, Sep 24, 1996

Filed:

Sep 27, 1995

Appl. No.:

8/534480

Inventors:

James P. Kardach - San Jose CA
Tosaku Nakanishi - Cupertino CA
Jimmy S. Cheng - Cupertino CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 108

US Classification:

395550

Abstract:

An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

US Patent:

59180439, Jun 29, 1999

Filed:

Jun 13, 1997

Appl. No.:

8/874559

Inventors:

James P. Kardach - San Jose CA
Tosaku Nakanishi - Cupertino CA
Jimmy S. Cheng - Cupertino CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 104
G06F 1100

US Classification:

395560

Abstract:

An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the/assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

US Patent:

55600026, Sep 24, 1996

Filed:

Sep 27, 1995

Appl. No.:

8/534596

Inventors:

James P. Kardach - San Jose CA
Tosaku Nakanishi - Cupertino CA
Jimmy S. Cheng - Cupertino CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 114

US Classification:

395550

Abstract:

An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

US Patent:

54737672, Dec 5, 1995

Filed:

Nov 3, 1992

Appl. No.:

7/970576

Inventors:

James P. Kardach - San Jose CA
Tosaku Nakanishi - Cupertino CA
Jimmy S. Cheng - Cupertino CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 106
G06F 1100

US Classification:

395550

Abstract:

An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

US Patent:

56574835, Aug 12, 1997

Filed:

Sep 27, 1995

Appl. No.:

8/534575

Inventors:

James P. Kardach - San Jose CA
Tosaku Nakanishi - Cupertino CA
Jimmy S. Cheng - Cupertino CA

International Classification:

G01F 132

US Classification:

395560

Abstract:

An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.