Jin Zhao

US Patent:

20060165784, Jul 27, 2006

Filed:

Mar 17, 2005

Appl. No.:

11/081780

Inventors:

Jin Zhao - Pasadena CA, US

International Classification:

A61K 9/20
A61K 33/10

US Classification:

424464000, 424687000

Abstract:

A dissoluble oral tablet of calcium supplement and the method of making the product are provided. This calcium supplement comprises an exposure area and a coating covered area. The surface ratio between the exposure area and the coating covered area is about 1:1 to 1:12. The exposure area can be a hole, an opening, or their combination. The preferred samples contain about CaCO3 200-600 mg with MgCL2 50-150 mg or MgSO4 50-100 mg. The favorable CaCO3 tablet reaction with stomach acid is: CaCO3+2HCL=CaCL2+H2CO3=Ca+2CL+H2O+CO2 ↑. The CO2 is the natural bubble broker. The stomach HCL is the natural CaCL2 maker.

US Patent:

56002840, Feb 4, 1997

Filed:

Oct 16, 1995

Appl. No.:

8/543740

Inventors:

Trung T. Nguyen - San Jose CA
Jin Zhao - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03B 504
H03B 524

US Classification:

331177R

Abstract:

A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing. All of which contribute to improved phase locked loop reliability especially when operating near the ends of the operating range.

US Patent:

56752946, Oct 7, 1997

Filed:

Jan 4, 1996

Appl. No.:

8/582881

Inventors:

Jyn-Bang Shyu - Cupertino CA
Jin Zhao - Milpitas CA

Assignee:

Sierra Semiconductor - San Jose CA

International Classification:

H03B 536

US Classification:

331 75

Abstract:

A single pin integrated oscillator circuit includes an amplifier having a first input terminal to which an external crystal may be connected, and a second input terminal which receives a feedback path from an output terminal of the amplifier. An oscillator output signal having a relatively large voltage swing is provided from the first input terminal through a buffer. The oscillator operates over a wide range of voltages and process variations, and it can accept an input signal from an external crystal or can accept any clock signal having a swing of approximately 1 V.

US Patent:

54691206, Nov 21, 1995

Filed:

Dec 7, 1994

Appl. No.:

8/351636

Inventors:

Trung T. Nguyen - San Jose CA
Jin Zhao - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03B 504
H03B 524
H03L 100
H03L 7099

US Classification:

331177R

Abstract:

A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing. All of which contribute to improved phase locked loop reliability especially when operating near the ends of the operating range.

US Patent:

20210127483, Apr 29, 2021

Filed:

Jan 4, 2021

Appl. No.:

17/247989

Inventors:

- Palo Alto CA, US
Aydin Nabovati - Redwood City CA, US
Jin Zhao - San Jose CA, US

International Classification:

H05K 1/02
H02J 1/12
G05F 1/10

Abstract:

A high-power Voltage Regulator Module (VRM) includes a housing having side walls, an upper opening, and a lower opening, a VRM circuit board oriented within the housing, a plane of the VRM circuit board oriented in parallel to at least one of the side walls of the housing, an upper Printed Circuit Board (PCB) coupled to the upper opening of the housing, a lower panel coupled to the lower opening of the housing, a coolant inlet port formed in the lower panel, and a coolant outlet port formed in the lower panel. The high power VRM may include a coolant inlet adapter coupled to the coolant inlet port and a coolant outlet adapter coupled to the coolant outlet port. The coolant inlet adapter and the coolant outlet adapter may provide support for the VRM.

US Patent:

20200053876, Feb 13, 2020

Filed:

Aug 7, 2018

Appl. No.:

16/056906

Inventors:

- Santa Clara CA, US
Jin Zhao - San Jose CA, US

International Classification:

H05K 1/02
H05K 1/18
H05K 1/09
H05K 1/03

Abstract:

A flexible printed circuit board (PCB) includes a flexible first layer proximate to a flexible second layer. Conductive traces are arranged in the flexible first layer and coupled to a first circuit block at a first end of the flexible PCB and coupled to a second circuit block at a second end of the flexible PCB such that the first circuit block is coupled to the second circuit block through the conductive traces. Companion traces re arranged in the flexible second layer to provide a reference plane coupled to the first and second circuit blocks. The companion traces are arranged in the flexible second layer to be replicas of the conductive traces such that each one of the conductive traces is proximate to and aligned with a corresponding one of the companion traces along an entire length between the first and second circuit blocks.

US Patent:

20190297723, Sep 26, 2019

Filed:

Mar 18, 2019

Appl. No.:

16/356037

Inventors:

- Palo Alto CA, US
Aydin Nabovati - Redwood City CA, US
Jin Zhao - San Jose CA, US

Assignee:

Tesla, Inc. - Palo Alto CA

International Classification:

H05K 1/02
G05F 1/10
H02J 1/12

Abstract:

A high-power Voltage Regulator Module (VRM) includes a housing having side walls, an upper opening, and a lower opening, a VRM circuit board oriented within the housing, a plane of the VRM circuit board oriented in parallel to at least one of the side walls of the housing, an upper Printed Circuit Board (PCB) coupled to the upper opening of the housing, a lower panel coupled to the lower opening of the housing, a coolant inlet port formed in the lower panel, and a coolant outlet port formed in the lower panel. The high power VRM may include a coolant inlet adapter coupled to the coolant inlet port and a coolant outlet adapter coupled to the coolant outlet port. The coolant inlet adapter and the coolant outlet adapter may provide support for the VRM.

US Patent:

20150230338, Aug 13, 2015

Filed:

Apr 20, 2015

Appl. No.:

14/691468

Inventors:

- SANTA CLARA CA, US
Jin Zhao - San Jose CA, US
John T. Vu - Hillsboro OR, US

International Classification:

H05K 1/18
H05K 1/03
H05K 1/11
H05K 3/32
H05K 3/42

Abstract:

Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.