Jing Han

US Patent:

20080273031, Nov 6, 2008

Filed:

Jul 15, 2008

Appl. No.:

12/218588

Inventors:

Pingping Shao - Cupertino CA, US
Jiangbo Zhang - Mountain View CA, US
Guofang Jiao - San Diego CA, US
Jing Han - San Jose CA, US
Tao Wang - Sunnyvale CA, US
Ben (Hsueh-Ban) Lan - Cupertino CA, US
Lingjun Chen - San Diego CA, US

International Classification:

G06T 17/00

US Classification:

345420

Abstract:

A method of rendering 3D graphics image includes the steps of: storing the primitives information into the primitive bank and parameter bank whose entries are made up the primitive IDs; converting the primitives into the pages whose coordinates are made up the page IDs; matching incoming page IDs of the incoming primitive with the page IDs stored in the page RAM in such a manner that when the incoming page ID of the incoming primitive matches with the sorted page ID stored in the page RAM, the incoming primitive are added to the corresponding page node in the page RAM under the corresponding page ID; flushing the page RAM when the free page nodes of the page RAM less than a predetermined amount or when the primitive's counter of the page node reaches another predetermined number; and rendering the primitives stored in the page memory into pixels.

US Patent:

20060187229, Aug 24, 2006

Filed:

Dec 8, 2005

Appl. No.:

11/299142

Inventors:

Pingping Shao - San Jose CA, US
Jiangbo Zhang - Mountain View CA, US
Guofang Jiao - San Jose CA, US
Jing Han - Santa Clara CA, US
Tao Wang - Sunnyvale CA, US
Ben Lan - Cupertino CA, US
Lingjun Chen - San Diego CA, US

International Classification:

G09G 5/36

US Classification:

345553000, 345557000

Abstract:

A method of rendering 3D graphics image using page based rendering technique includes the steps of: dividing a plurality of primitives having respective primitive ID into a plurality of pages having respective page ID; sorting the primitives for each of the pages, and storing the sorted primitives into a page RAM under a plurality of page nodes which correspond with the sorted page IDs; matching incoming page IDs of the incoming primitive IDs with the page IDs stored in the page RAM in such a manner that when the incoming page ID of the incoming primitive matches with the sorted page ID stored in the page RAM, the incoming primitive are stored at the corresponding page node in the page RAM under the corresponding page ID; and rendering the primitives stored in the page memory into pixels displayed on the display screen.

US Patent:

20210103308, Apr 8, 2021

Filed:

Nov 20, 2020

Appl. No.:

17/100603

Inventors:

- Santa Clara CA, US
Harish Krishnamurthy - Beaverton OR, US
Krishnan Ravichandran - Saratoga CA, US
Vivek De - Beaverton OR, US
Scott Chiu - Folsom CA, US
Claudia Patricia Barrera Gonzalez - Campbell CA, US
Jing Han - Mountain View CA, US
Rajasekhara Madhusudan Narayana Bhatla - Santa Clara CA, US

International Classification:

G05F 1/56
G05F 1/46
G05F 1/67

Abstract:

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

US Patent:

20190317536, Oct 17, 2019

Filed:

Jun 24, 2019

Appl. No.:

16/450873

Inventors:

- Santa Clara CA, US
Harish Krishnamurthy - Beaverton OR, US
Krishnan Ravichandran - Saratoga CA, US
Vivek De - Beaverton OR, US
Scott Chiu - Folsom CA, US
Claudia Patricia Barrera Gonzalez - Campbell CA, US
Jing Han - Mountain View CA, US
Rajasekhara Madhusudan Narayana Bhatla - Santa Clara CA, US

International Classification:

G05F 1/56
G05F 1/67
G05F 1/46

Abstract:

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.