John Ka Chan

US Patent:

6594036, Jul 15, 2003

Filed:

May 28, 1998

Appl. No.:

09/086785

Inventors:

Sau C. Wong - Hillsborough CA
Leo Petropoulos - San Jose CA
John H. Chan - Cupertino CA

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

H04N 140

US Classification:

358471, 348254

Abstract:

A digital imaging system uses an analog/multi-level memory to store image data. The stored analog/multi-level data can then be accessed directly by an analog device or the data can be accessed by an A/D converter for conversion to a digital format. The digital data is then routed to any number of desired digital devices. By using an analog/multi-level memory instead of a digital memory to store image data, problems associated with storing large amounts of digital data are minimized or eliminated, such as loss of information from image compression and high costs of large digital memories and signal processing and compression circuits.

US Patent:

20120225063, Sep 6, 2012

Filed:

Mar 5, 2012

Appl. No.:

13/412610

Inventors:

John K. Chan - Foster City CA, US

International Classification:

A61K 39/395
C12Q 1/02
C40B 30/00
C12Q 1/68
A61P 35/00
A61P 9/00

US Classification:

4241331, 506 7, 435 61, 435 29

Abstract:

Methods are provided for selecting and treating patients with an anti-angiogenic agent and methods for reducing the risk of adverse events in patients from treatment with an anti-angiogenic agent, comprising the steps: obtaining a sample of tumor and normal tissues from a patient; determining the miRNA or protein expression in said samples; comparing the miRNA or protein expression in said tumor sample to the miRNA or protein expression in normal tissue; determining whether said tumor miRNA or protein expression is higher or lower than said normal miRNA or protein expression, wherein if said miRNA or protein expression indicates that the expression of at least one angiogenic gene is upregulated, the patient is scheduled for treatment with an anti-angiogenic agent. Preferably the anti-angiogenic agent is a VEGF-targeting agent or a tyrosine kinase inhibitor. In preferred embodiments, the VEGF-targeting agent is bevacizumab.

US Patent:

58597948, Jan 12, 1999

Filed:

Jun 13, 1997

Appl. No.:

8/874794

Inventors:

John Y. Chan - San Carlos CA

Assignee:

NuRam Technology, Inc. - Santa Clara CA

International Classification:

G11C 1124

US Classification:

365149

Abstract:

A dynamic random access memory device stores two bits of digital data in each memory cell. Two sense amplifiers are provided to sense and reproduce any of the four binary values 11, 10, 01, 00 representing a strong one, a weak one, a weak zero and a strong zero, respectively, capable of being stored in each cell. The signal read out of a memory cell is restored to the memory cell by a feedback circuit which utilizes the outputs of the sense amplifiers. Thus the proper charge is replaced on the selected storage capacitor in the memory cell.

US Patent:

48377481, Jun 6, 1989

Filed:

Apr 14, 1987

Appl. No.:

7/038107

Inventors:

Shine C. Chung - San Jose CA
Siu K. Tsang - San Jose CA
James T. Koo - Los Altos Hills CA
Sho Long S. Chen - Palo Alto CA
John Y. Chan - San Carlos CA

Assignee:

Vitelic Corporation - San Jose CA

International Classification:

G11C 800

US Classification:

365236

Abstract:

An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.

US Patent:

43707378, Jan 25, 1983

Filed:

Feb 11, 1980

Appl. No.:

6/120426

Inventors:

John Y. Chan - Belmont CA

Assignee:

Fairchild Camera and Instrument Corporation - Mountain View CA

International Classification:

G11C 1124

US Classification:

365203

Abstract:

A sense amplifier for determining the binary logic state of a dynamic memory cell (11. sub. x,y) preamplifies an initial voltage difference established between a first input line (17. sub. y) coupled to the memory cell (11. sub. x,y) and a first reference line (18. sub. y) coupled to a reference cell (32. sub. y). The resulting amplifies voltage difference is generated between a second input line (19) coupled through a coupling device (Q51. sub. y) to the first input line (17. sub. y) and a second reference line (20) coupled through another coupling device (Q52. sub. y) to the first reference line (18. sub. y) by capacitively charging the second lines (19 and 20) preferably with a pair of capacitors (C61 and C62) individually coupled to the second lines (19 and 20). A differential sensing device (90) senses the amplified voltage difference to determine the logic state which is fully restored to the memory cell (11. sub. x,y).

US Patent:

56444516, Jul 1, 1997

Filed:

May 26, 1995

Appl. No.:

8/451632

Inventors:

John R. Chan - Fremont CA
Jeffrey R. Burt - Mountain View CA

Assignee:

Samsung Information Systems America, Inc. - Santa Clara County CA

International Classification:

G11B 554

US Classification:

360105

Abstract:

Mechanisms for loading and unloading heads on surfaces of disks in a disk drive provide ramps attached to central portions of the disks. The ramps are integral parts of spacers between disks or spacers or disk clamps at the top or bottom of a stack of disks. Each head assembly has a suspension arm that engages a corresponding ramp to lift a read/write head away from a surface of a disk. Heads land (or return to the surfaces of the disks) in landing zones at inner diameters of the disks and do not damage data because the loading zones contain no data storage. Alignment of the ramps with the disks is automatic because ramps directly attach to the disks.

US Patent:

47033754, Oct 27, 1987

Filed:

Nov 22, 1985

Appl. No.:

6/801143

Inventors:

John R. Chan - Fremont CA
Homer S. Pitner - Santa Clara CA

Assignee:

Chan Industries, Inc. - Santa Clara CA

International Classification:

G11B 554
G11B 2122

US Classification:

360105

Abstract:

An improved magnetic head carriage and support apparatus including a carriage body a lower head supporting arm affixed to the carriage body and carrying a gimbaled mounted lower head, an upper arm pivotally connected to the carriage body and movable between a retracted position and a media engaging position in which a stop is engaged. The upper arm carries an upper head that is also gimbal mounted and head load is applied by a light weight flexure spring such that when the upper arm is in the media engaging position the head are free to move relative to the supporting arms as either the media moves out of it mid-plane or the carriage moves towards or away from the media mid-plane.

US Patent:

43119301, Jan 19, 1982

Filed:

Dec 17, 1979

Appl. No.:

6/104639

Inventors:

John Y. Chan - Belmont CA
John J. Barnes - Fremont CA

Assignee:

Fairchild Camera & Instrument Corp. - Mountain View CA

International Classification:

H03K 1716
H03K 17687

US Classification:

307575

Abstract:

A voltage protection circuit for controlling an input data signal on a signal-carrying line to a binary data-storage device having an input line for receiving the input data signal comprises two transistors in series having current-control electrodes coupled to an input control terminal and a third transistor having its current-control electrode coupled to the input line with one current-conducting electrode coupled to a voltage source and another current-conducting electrode coupled to current-conducting electrodes of the first two transistors.