John Casey Duncan

US Patent:

8013649, Sep 6, 2011

Filed:

Oct 7, 2009

Appl. No.:

12/574798

Inventors:

John L. Duncan - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

H03K 3/356

US Classification:

327203, 327199, 327218, 326 93

Abstract:

A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.

US Patent:

8438367, May 7, 2013

Filed:

Oct 1, 2009

Appl. No.:

12/572052

Inventors:

Thomas C. McDonald - Austin TX, US
John L. Duncan - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 9/40

US Classification:

712210

Abstract:

An apparatus has a queue, each entry stores a different line of a stream of instruction bytes and accumulated prefix information associated with each instruction byte. Control logic: (a) detects a condition where an initial portion of an instruction partially within a first line stored in the bottom entry (BE) of the queue remains unextracted from the queue, wherein the initial portion instruction bytes are all prefix bytes; (b) saves away the initial portion length, shifts the first line in the BE out of the queue, and shifts a second line into the BE, in response to detecting the condition; (c) extracts instruction bytes of the unextracted instruction from the second line in the BE and extracts accumulated prefix information from the second line of the BE in place of the already shifted out initial portion prefix bytes; (d) calculates the unextracted instruction length using the saved length; and (e) extracts an instruction other than the unextracted instruction from the second line in the BE using the calculated length.

US Patent:

8443172, May 14, 2013

Filed:

Oct 1, 2009

Appl. No.:

12/571997

Inventors:

Thomas C. McDonald - Austin TX, US
John L. Duncan - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 9/30

US Classification:

712210, 712212

Abstract:

An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes. If during the first clock cycle and any of N subsequent clock cycles the decode logic indicates that one of the predetermined number of instruction bytes specifies a length-modifying prefix, the operand/address size logic provides to the decode logic on the next clock cycle the address/operand size specified by the length-modifying prefix to use to generate the start and end marks.

US Patent:

8533434, Sep 10, 2013

Filed:

Oct 1, 2009

Appl. No.:

12/572045

Inventors:

John L. Duncan - Austin TX, US
Thomas C. McDonald - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 9/30

US Classification:

712210

Abstract:

An apparatus efficiently determines the length of an instruction within a stream of instruction bytes processed by a microprocessor having a variable instruction length instruction set architecture. The apparatus includes combinatorial logic associated with each instruction byte of the stream, each configured to receive the associated instruction byte and the next instruction byte of the stream and to generate in response thereto a first length, a second length, and a select control. A multiplexor associated with each of the combinatorial logic selects and outputs one of the following inputs based on the select control received from the combinatorial logic: a zero input and the second length received from the combinatorial logic associated with each of the next three instruction bytes of the stream. An adder associated with each of the combinatorial logic and multiplexor adds the first length and the output of the multiplexor to generate the length of the instruction.

US Patent:

8612727, Dec 17, 2013

Filed:

Oct 1, 2009

Appl. No.:

12/571997

Inventors:

Thomas C. McDonald - Austin TX, US
John L. Duncan - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 9/30

US Classification:

712210, 712212

Abstract:

An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes. If during the first clock cycle and any of N subsequent clock cycles the decode logic indicates that one of the predetermined number of instruction bytes specifies a length-modifying prefix, the operand/address size logic provides to the decode logic on the next clock cycle the address/operand size specified by the length-modifying prefix to use to generate the start and end marks.

US Patent:

20100299500, Nov 25, 2010

Filed:

Oct 1, 2009

Appl. No.:

12/572002

Inventors:

Thomas C. McDonald - Austin TX, US
John L. Duncan - Austin TX, US

Assignee:

VIA Technologies, Inc. - Taipei

International Classification:

G06F 9/30

US Classification:

712208, 712E09028

Abstract:

In a microprocessor that has an instruction set architecture in which the instructions may include a variable number of prefix bytes, an apparatus for efficiently extracting instructions from a stream of undifferentiated instruction bytes. Decode logic determines which byte is an opcode byte for each instruction of a plurality of instructions within the stream of undifferentiated instruction bytes. The opcode byte is the first non-prefix byte of the instruction. The decode logic accumulates prefix information onto the opcode byte of the instruction for each instruction of the plurality of instructions. A queue holds the stream of undifferentiated instruction bytes and the accumulated prefix information. Extraction logic extracts the plurality of instructions from the queue in one clock cycle independent of the number of prefix bytes included in each of the plurality of instructions.

US Patent:

58926992, Apr 6, 1999

Filed:

Sep 16, 1997

Appl. No.:

8/931859

Inventors:

John L. Duncan - Austin TX
Albert J. Loper - Cedar Park TX

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G06F 752

US Classification:

36476001

Abstract:

A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.

US Patent:

55507743, Aug 27, 1996

Filed:

Sep 5, 1995

Appl. No.:

8/523663

Inventors:

Michael L. Brauer - Austin TX
Paul A. Reed - Austin TX
John L. Duncan - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 800

US Classification:

36518902

Abstract:

A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48, 50, 52, 54). The memory cache executes a parallel tag and data array access but does not enable any sense amplifier until a comparator indicates a cache hit. Consequently, the memory cache is suitable for use where power consumption and speed are equally important design constraints.