John Robert Mcgowan

US Patent:

6362649, Mar 26, 2002

Filed:

Apr 2, 1999

Appl. No.:

09/286128

Inventors:

John E. McGowan - Sunnyvale CA

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39, 326 40

Abstract:

A hybrid integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input/output pads of the first group is connected to an output of one of the output buffer circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the output and input buffer circuits from the mask programmable portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input/output pads and selected ones of the interconnect conductors, intersections with outputs of the input buffer circuits and selected ones of the interconnect conductors, and intersections with the inputs of the output buffer circuits and selected ones of the interconnect conductors.

US Patent:

59528524, Sep 14, 1999

Filed:

Jul 2, 1997

Appl. No.:

8/887380

Inventors:

John E. McGowan - Sunnyvale CA
William C. Plants - Santa Clara CA
Warren K. Miller - Palo Alto CA

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 19177
H03K 1908

US Classification:

326106

Abstract:

In a first aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a test probe circuit associated with a column in the array, selecting at least one logic module associated with the test probe circuit, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred. In a second aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a plurality of test probe circuits, each associated with a column in the array, selecting at least one logic module associated with each of the test probe circuits, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred.

US Patent:

58217762, Oct 13, 1998

Filed:

Jan 31, 1997

Appl. No.:

8/792902

Inventors:

John E. McGowan - Sunnyvale CA

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

326 41

Abstract:

A mixed signal integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed analog function circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the analog function circuits, and one of the input/output pads of the first group is connected to an output of one of the analog function circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the analog function circuits from the mask programmable analog portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input/output pads and selected ones of the interconnect conductors, intersections with outputs of the analog function circuits and selected ones of the interconnect conductors, and intersections with the inputs of the analog function circuits and selected ones of the interconnect conductors.

US Patent:

57449805, Apr 28, 1998

Filed:

Feb 16, 1996

Appl. No.:

8/603597

Inventors:

John E. McGowan - Sunnyvale CA
William C. Plants - Santa Clara CA
Joel D. Landry - Colorado Springs CO
Sinan Kaptanoglu - San Carlos CA
Warren K. Miller - Palo Alto CA

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 19177

US Classification:

326 40

Abstract:

A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof.

US Patent:

59594667, Sep 28, 1999

Filed:

Jan 31, 1997

Appl. No.:

8/792482

Inventors:

John E. McGowan - Sunnyvale CA

Assignee:

Actel Corporation - Sunnyvale CA

International Classification:

H03K 738

US Classification:

326 39

Abstract:

A hybrid integrate circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input/output pads of the first group is connected to an output of one of the output buffer circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the output and input buffer circuits from the mask programmable portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input/output pads and selected ones of the interconnect conductors, intersections with outputs of the input buffer circuits and selected ones of the interconnect conductors, and intersections with the inputs of the output buffer circuits and selected ones of the interconnect conductors.