John A Reinert

US Patent:

41258770, Nov 14, 1978

Filed:

Nov 26, 1976

Appl. No.:

5/745023

Inventors:

John R. Reinert - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 700
G11C 1140

US Classification:

365190

Abstract:

A dual port memory cell suitable for use in emitter coupled logic applications is accessible from two different address ports. The dual port storage cell includes first and second cross coupled cells, each including a selection conductor and a pair of diodes coupled to the cross coupled transistors to effect selection of that storage cell. The base of each of the cross coupled transistors of the first storage cell is coupled to the base of a coupling transistor, the emitter of which is connected to the base of a corresponding transistor of the other storage cell. Each dual port memory cell has two pairs of bit lines, one pair being coupled to the first storage cell and the other being coupled to the second storage cell. If one of the storage cells is selected, and the other remains unselected, the information in the selected cell is automatically written into the unselected storage cell.

US Patent:

40990702, Jul 4, 1978

Filed:

Nov 26, 1976

Appl. No.:

5/745021

Inventors:

John R. Reinert - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 700
G11C 1140
H03K 3286
H03K 3353

US Classification:

307238

Abstract:

A sense-write circuit for use with a emitter coupled logic memory array is provided. A first differential stage includes a pair of emitter-coupled transistors connected to a current source controlled by a chip select voltage. A first one of the emitter-coupled transistors has its base connected to a first reference voltage and the second one of said transistors has its base coupled to a write enable input. The collector of a first one of the emitter-coupled transistors serves as a current source for a second differential stage including a second pair of emitter-coupled transistors, a first one having its base connected to a second reference voltage and the second having its base coupled to a data input conductor. The two respective outputs of the second differential stage are coupled to emitter follower drivers, and are also independently coupled through a pair of respective diode-connected transistors to the collector of the first transistor of the first emitter coupled pair.

US Patent:

40853411, Apr 18, 1978

Filed:

Dec 20, 1976

Appl. No.:

5/752484

Inventors:

John Robert Reinert - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1908

US Classification:

307247R

Abstract:

An integrated injection logic storage element having a minimum delay time. Means for steering input data into the circuit are provided. These means are coupled to another means for selectively gating the input data through the circuit. The means for selectively gating is responsive to a clock pulse. A third means for providing an output storage latch and having multiple outputs is coupled to the means for selectively gating. At least one of the multiple outputs is coupled to an output of the means for selectively gating thereby providing an output which has a delay time which is less than another one of the multiple outputs which is not coupled to the means for selectively gating.