John A Weber

US Patent:

7712343, May 11, 2010

Filed:

Sep 1, 2005

Appl. No.:

11/218113

Inventors:

Jerry Smith - Littleton CO, US
Mike Enslow - Milwaukee WI, US
Dean D. Hacker - Oak Creek WI, US
John Weber - Thiensville WI, US
Tim Ebner - Menomonee Falls WI, US
Jesse Marcelle - Muskego WI, US

Assignee:

Master Lock Company LLC - Oak Creek WI

International Classification:

E05B 55/04
E05B 13/10

US Classification:

70467, 70483, 70224, 292359

Abstract:

A deadbolt mechanism including a lock out mechanism that functions to disable the operation of the deadbolt from at least one side of the deadbolt mechanism. The deadbolt mechanism includes a deadbolt, key cylinder, housing, turn knob and a shaft that connects the key cylinder and turn knob. To place the deadbolt mechanism in lock out mode, a release mechanism is actuated and the turn knob is pulled outward away from the door. By pulling the knob outward, the shaft engages a portion of the housing which prevents rotation of the shaft and thereby prevents movement of the deadbolt from the lock-out position.

US Patent:

20190171824, Jun 6, 2019

Filed:

Feb 8, 2019

Appl. No.:

16/270764

Inventors:

- Armonk NY, US
SHAILESH R. GAMI - POUGHKEEPSIE NY, US
JOHN L. WEBER - TILLSON NY, US
DENNIS WITTIG - POUGHKEEPSIE NY, US

International Classification:

G06F 21/57
G06F 11/36
G06F 21/53

Abstract:

A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.

US Patent:

20180173880, Jun 21, 2018

Filed:

Dec 15, 2016

Appl. No.:

15/379772

Inventors:

- ARMONK NY, US
Shailesh R. Gami - Poughkeepsie NY, US
John L. Weber - Tillson NY, US
Dennis Wittig - Poughkeepsie NY, US

International Classification:

G06F 21/57
G06F 11/36
G06F 9/455
G06F 21/53

Abstract:

A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.