Jonathan Stephen Hacker

US Patent:

20230104042, Apr 6, 2023

Filed:

Dec 12, 2022

Appl. No.:

18/079183

Inventors:

- Boise ID, US
Jonathan S. Hacker - Meridian ID, US

International Classification:

H01L 23/00
H01L 25/065
H01L 25/00
G06F 30/394

Abstract:

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

US Patent:

20210257226, Aug 19, 2021

Filed:

Apr 12, 2021

Appl. No.:

17/227525

Inventors:

- Boise ID, US
Jonathan S. Hacker - Meridian ID, US

International Classification:

H01L 21/56
H01L 23/31
H01L 23/00

Abstract:

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

US Patent:

20210074663, Mar 11, 2021

Filed:

Nov 23, 2020

Appl. No.:

17/102253

Inventors:

- Boise ID, US
Jonathan S. Hacker - Meridian ID, US

International Classification:

H01L 23/00
H01L 25/065
H01L 25/00
G06F 30/394

Abstract:

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

US Patent:

20210041495, Feb 11, 2021

Filed:

Oct 28, 2020

Appl. No.:

17/083193

Inventors:

- Boise ID, US
Kurt J. Bossart - Eagle ID, US
Jonathan S. Hacker - Meridian ID, US
Chandra S. Tiwari - Boise ID, US

International Classification:

G01R 31/28
H01L 21/67
G01R 1/073
H01L 21/68

Abstract:

A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3D interconnect (3DI) structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

US Patent:

20200373252, Nov 26, 2020

Filed:

Aug 14, 2020

Appl. No.:

16/993860

Inventors:

- Boise ID, US
Wei Zhou - Boise ID, US
Christopher J. Gambee - Caldwell ID, US
Jonathan S. Hacker - Meridian ID, US
Shijian Luo - Boise ID, US

International Classification:

H01L 23/00
H01L 25/065
H01L 25/00

Abstract:

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

US Patent:

20200206869, Jul 2, 2020

Filed:

Dec 31, 2018

Appl. No.:

16/237051

Inventors:

- Boise ID, US
Jonathan S. Hacker - Meridian ID, US

International Classification:

B24B 53/017
B24B 53/07
B24B 53/12
B24B 37/02

Abstract:

A dressing board for sharpening and/or shaping blades for manufacture of semiconductor devices can include a working surface configured to sharpen and/or shape a cutting surface of a dicing or edging blade for manufacture of a semiconductor device. The working surface can be configured to contact the cutting surface of the blade when sharpening or shaping the cutting surface. The dressing board can include a support substrate configured to support the working surface with respect to a floor of an enclosure in which the dressing board is positioned. In some embodiments, the working surface includes a first portion that is not parallel to the floor.

US Patent:

20200083178, Mar 12, 2020

Filed:

Sep 11, 2018

Appl. No.:

16/127769

Inventors:

- Boise ID, US
Wei Zhou - Boise ID, US
Christopher J. Gambee - Caldwell ID, US
Jonathan S. Hacker - Meridian ID, US
Shijian Luo - Boise ID, US

International Classification:

H01L 23/00
H01L 25/065
H01L 25/00

Abstract:

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

US Patent:

20190385967, Dec 19, 2019

Filed:

Aug 23, 2019

Appl. No.:

16/550045

Inventors:

- Boise ID, US
Jonathan S. Hacker - Meridian ID, US

International Classification:

H01L 23/00
G06F 17/50
H01L 25/00
H01L 25/065

Abstract:

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.